87C196CA87C196CB

t e 1 state time (125 ns

16 MHz)

NORMAL MASTERSLAVE OPERATION

Symbol

Parameter

Min

Max

Units

Clock Period

4t

ns

Clock Low TimeClock High Time

2t b10

Clock Falling to Data Out Valid (Master)

05t

15t a 20

ns

Clock Falling to Data Out Valid (Slave)

05t

15t a 50

ns

Data In Setup to Clock Rising Edge

10

ns

Clock Rising Edge to Data in Invalid

t a 15

ns

Timings are guaranteed by design

HANDSHAKE OPERATION

Symbol

Parameter

Min

Max

Units

Clock Period

4t

ns

Clock Low TimeClock High Time

2t b10

Clock Falling to Data Out Valid (Master)

05t

15t a 20

ns

Clock Falling to Data Out Valid (Slave)

05t

15t a 50

ns

Data In Setup to Clock Rising Edge

10

ns

Clock Rising Edge to Data in Invalid

t a 15

ns

Timings are guaranteed by design

NOTE

1 This specification refers to input clocks during slave operation During master operation the device will output a nominal

50% duty cycle clock

272405 – 34

NOTE

The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal

The SCx signal will be different for other configurations however setup and hold timings will still be the same in relation

to the latching edge of SCx

Figure 6 Synchronous Serial Port

23