VE28F008

Table 3 Command Definitions

Command

Cycles

Req’d

Bus

Notes

First Bus Cycle

Second Bus Cycle

Operation Address Data Operation Address Data

Read ArrayReset

1

1

Write

X

FFH

Intelligent Identifier

3

2 3 4

Write

X

90H

Read

IA

IID

Read Status Register

2

3

Write

X

70H

Read

X

SRD

Clear Status Register

1

Write

X

50H

Erase SetupErase Confirm

2

2

Write

BA

20H

Write

BA

D0H

Erase SuspendErase Resume

2

Write

X

B0H

Write

X

D0H

Byte Write SetupWrite

2

2 3 5

Write

WA

40H

Write

WA

WD

Alternate Byte Write SetupWrite

2

2 3 5

Write

WA

10H

Write

WA

WD

NOTES

1 Bus operations are defined in Table 2

4 Following the intelligent identifier command two read operations access manufacture and device codes

5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command

6 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

Write

Writes to the Command User Interface enable read-

ing of device data and intelligent identifier They also

control inspection and clearing of the Status Regis-

User Interface controls block erasure and byte write

The contents of the interface register serve as input

to the internal write state machine

The Command User Interface itself does not occupy

an addressable memory location The interface reg-

ister is a latch used to store the command and ad-

dress and data information needed to execute the

command Erase Setup and Erase Confirm com-

mands require both appropriate command data and

an address within the block to be erased The Byte

Write Setup command requires both appropriate

command data and the address of the location to be

written while the Byte Write command consists of

the data to be written and the address of the loca-

tion to be written

The Command User Interface is written by bringing

dresses and data are latched on the rising edge of

WE

Standard microprocessor write timings are

used

Refer to AC Write Characteristics and the AC Wave-

forms for Write Operations Figure 9 for specific tim-

ing parameters

COMMAND DEFINITIONS

tions from the Status Register intelligent identifier

enables successful byte write and block erase oper-

ations as well

Device operations are selected by writing specific

commands into the Command User Interface Table

3 defines the VE28F008 commands

Read Array Command

Upon initial device powerup and after exit from deep

powerdown mode the VE28F008 defaults to Read

Array mode This operation is also initiated by writing

FFH into the Command User Interface Microproces-

sor read cycles retrieve array data The device re-

mains enabled for reads until the Command User

Interface contents are altered Once the internal

Write State Machine has started a block erase or

byte write operation the device will not recognize

8