28F008SA datasheet(3/26 Pages) INTEL

3 / 26 page

VE28F008

271305 – 1

Figure 1 Block Diagram

Table 1 Pin Description

Symbol

Type

Name and Function

A0–A19

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally

latched during a write cycle

DQ0–DQ7

INPUTOUTPUT

DATA INPUTOUTPUTS

Inputs data and commands during Command

User Interface write cycles outputs data during memory array Status

float to tri-state off when the chip is deselected or the outputs are

disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device’s control logic input buffers

decoders and sense amplifiers CE is active low CE high deselects the

memory device and reduces power consumption to standby levels

INPUT

RESETDEEP POWERDOWN

Puts the device in the deep powerdown

mode RP is active low RP high gates normal operation RP also locks

out block erase or byte write operations when active low providing data

protection during power transitions RP active resets internal

automation Exit from Deep Powerdown sets device to read-array mode

INPUT

OUTPUT ENABLE

Gates the device’s outputs through the data buffers

during a read cycle OE is active low

INPUT

WRITE ENABLE

Controls writes to the Command User Interface and

array blocks WE is active low Addresses and data are latched on the

rising edge of the WE pulse

28F008SA Datasheet(PDF) 3 Page - Intel Corporation