28F008SA datasheet(23/26 Pages) INTEL

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VE28F008

ALTERNATIVE CE-CONTROLLED WRITES(1)

Symbol

Parameter

Notes

VE28F008-95(6)

Unit

Min

Max

tAVAV

tWC

Write Cycle Time

tPHEL

tPS

RP High Recovery to CE Going Low

tWLEL

tWS

WE Setup to CE Going Low

tELEH

tCP

CE Pulse Width

tVPEH

tVPS

VPP Setup to CE Going High

100

tAVEH

tAS

Address Setup to CE Going High

tDVEH

tDS

Data Setup to CE Going High

tEHDX

tDH

Data Hold from CE High

tEHAX

tAH

Address Hold from CE High

tEHWH

tWH

WE Hold from CE High

tEHEL

tEPH

CE Pulse Width High

tEHRL

CE High to RYBY Going Low

100

tEHQV1

Duration of Byte Write Operation

tEHQV2

Duration of Block Erase Operation

sec

tEHGL

Write Recovery before Read

tQVVL

tVPH

VPP Hold from Valid SRD RYBY High

2 5

NOTES

1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE

defines the write pulsewidth (within a longer WE timing waveform) all setup hold and inactive WE times should be mea-

sured relative to the CE waveform

2 Sampled not 100% tested

3 Refer to Table 3 for valid AIN for byte write or block erasure

4 Refer to Table 3 for valid DIN for byte write or block erasure

5 Byte write and block erase durations are measured to completion (SR7 e 1 RYBY e VOH) VPP should be held at

VPPH until determination of byte writeblock erase success (SR345 e 0)

6 See AC InputOutput Reference Waveforms and AC Testing Load Circuits for testing characteristics

28F008SA Datasheet(PDF) 23 Page - Intel Corporation

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