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28F008SA Datasheet(PDF) 5 Page - Intel Corporation |
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28F008SA Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 26 page ![]() VE28F008 271305 – 3 Figure 3 VE28F008 Array Interface to Intel386TM SL Microprocessor Superset through PI Bus (Including RYBY Masking and Selective Powerdown) for DRAM Backup during System SUSPEND Resident OS and Applications and Motherboard Solid-State Disk PRINCIPLES OF OPERATION The VE28F008 includes on-chip write automation to manage write and erase functions The Write State Machine allows for 100% TTL-level control inputs fixed power supplies during block erasure and byte write and minimal processor overhead with RAM- like interface timings After initial device powerup or after return from deep powerdown mode (see Bus Operations) the VE28F008 functions as a read-only memory Manip- ulation of external memory-control pins allow array read standby and output disable operations Both Status Register and intelligent identifier can also be accessed through the Command User Inter- face when VPP e VPPL This same subset of operations is also available when high voltage is applied to the VPP pin In addi- tion high voltage on VPP enables successful block erasure and byte writing of the device All functions associated with altering memory contentsbyte write block erase status and intelligent identifier are accessed via the Command User Interface and verified thru the Status Register Commands are written using standard microproces- sor write timings Command User Interface contents serve as input to the WSM which controls the block 5 |
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