8741AH datasheet(3/20 Pages) INTEL

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UPI-41AH42AH

Table 1 Pin Description

DIP

PLCC

Symbol

Type

Name and Function

TEST 0

TEST INPUTS

Input pins which can be directly tested using conditional branch

instructions

TEST 1

FREQUENCY REFERENCE

TEST 1 (T1) also functions as the event timer input (under

software control) TEST 0 (T0) is used during PROM programming and ROMEPROM

verification It is also used during Sync Mode to reset the instruction state to S1 and

synchronize the internal clock to PH1 See the Sync Mode Section

XTAL 1

INPUTS

Inputs for a crystal LC or an external timing signal to determine the internal

oscillator frequency

XTAL 2

RESET

Input used to reset status flip-flops and to set the program counter to zero

RESET is also used during EPROM programming and verification

SINGLE STEP

Single step input used in conjunction with the SYNC output to step the

program through each instruction (EPROM) This should be tied to a5V when not used

This pin is also used to put the device in Sync Mode by applying 125V to it

CHIP SELECT

Chip select input used to select one UPI microcomputer out of several

connected to a common data bus

EXTERNAL ACCESS

External access input which allows emulation testing and

ROMEPROM verification This pin should be tied low if unused

READ

IO read input which enables the master CPU to read data and status words from

the OUTPUT DATA BUS BUFFER or status register

910

COMMANDDATA SELECT

Address Input used by the master processor to indicate

whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0

during program and verify operations

WRITE

IO write input which enables the master CPU to write data and command words

to the UPI INPUT DATA BUS BUFFER

SYNC

OUTPUT CLOCK

Output signal which occurs once per UPI instruction cycle SYNC can

be used as a strobe for external circuitry it is also used to synchronize single step

operation

D0–D7

(BUS)

12–19 14–21

I O

DATA BUS

Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI

microcomputer to an 8-bit master system data bus

P10–P17 27–34 30–33

I O

PORT 1

8-bit PORT 1 quasi-bidirectional IO lines P10–P17 access the signature row

and security bit

35–38

P20–P27 21–24 24–27

I O

PORT 2

8-bit PORT 2 quasi-bidirectional IO lines The lower 4 bits (P20–P23) interface

directly to the 8243 IO expander device and contain address and data information during

35–38 39–42

PORT 4 – 7 access The upper 4 bits (P24–P27) can be programmed to provide interrupt

Request and DMA Handshake capability Software control can configure P24 as Output

Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request

(DRQ) and P27 as DMA ACKnowledge (DACK)

PROG

PROGRAM

Multifunction pin used as the program pulse input during PROM programming

During IO expander access the PROG pin acts as an addressdata strobe to the 8243

This pin should be tied high if unused

VCC

POWER a

5V main power supply pin

VDD

POWER a

5V during normal operation a125V during programming operation Low

power standby supply pin

VSS

GROUND

Circuit ground potential

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