8741AH datasheet(4/20 Pages) INTEL

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UPI-41AH42AH

UPI-41AH and UPI-42AH FEATURES

Two Data Bus Buffers one for input and one for

output This allows a much cleaner MasterSlave

protocol

210393 – 4

8 Bits of Status

ST7 ST6 ST5 ST4 F1 F0 IBF OBF

D4 D3 D2 D1

ST4–ST7 are user definable status bits These

bits are defined by the ‘‘MOV STS A’’ single byte

single cycle instruction Bits 4 – 7 of the acccumu-

lator are moved to bits 4 – 7 of the status register

Bits 0 – 3 of the status register are not affected

MOV STS A

Op Code 90H

001000

RD and WR are edge triggered IBF OBF F1 and

INT change internally after the trailing edge of RD

or WR

210393 – 6

During the time that the host CPU is reading the

status register the UPI is prevented from updat-

ing this register or is ‘locked out’

P24 and P25 are port pins or Buffer Flag pins

which can be used to interrupt a master proces-

sor These pins default to port pins on Reset

If the ‘‘EN FLAGS’’ instruction has been execut-

ed P24 becomes the OBF (Output Buffer Full) pin

A ‘‘1’’ written to P24 enables the OBF pin (the pin

outputs the OBF Status Bit) A ‘‘0’’ written to P24

disables the OBF pin (the pin remains low) This

pin can be used to indicate that valid data is avail-

able from the UPI (in Output Data Bus Buffer)

If ‘‘EN FLAGS’’ has been executed P25 becomes

the IBF (Input Buffer Full) pin A ‘‘1’’ written to P25

enables the IBF pin (the pin outputs the inverse of

the IBF Status Bit A ‘‘0’’ written to P25 disables

the IBF pin (the pin remains low) This pin can be

used to indicate that the UPI is ready for data

210393 – 5

Data Bus Buffer Interrupt Capability

EN FLAGS

Op Code 0F5H

11010

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