AD7918_15 datasheet(23/28 Pages) AD

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Data Sheet

AD7908/AD7918/AD7928

Rev. E | Page 23 of 28

POWER VS. THROUGHPUT RATE

By operating in auto shutdown mode on the AD7908/AD7918/

AD7928, the average power consumption of the ADC decreases

at lower throughput rates. Figure 25 shows how as the

throughput rate is reduced, the part remains in its shutdown

state longer and the average power consumption over time

drops accordingly.

For example, if the AD7928 is operated in a continuous

sampling mode with a throughput rate of 100 kSPS and an

SCLK of 20 MHz (AVDD = 5 V), and the device is placed in auto

shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the

power consumption is calculated as follows:

The maximum power dissipation during normal operation is

13.5 mW (AVDD = 5 V). If the power-up time from auto

shutdown is one dummy cycle, that is, 1 μs, and the remaining

conversion time is another cycle, that is, 1 μs, then the AD7928

can be said to dissipate 13.5 mW for 2 μs during each

conversion cycle. For the remainder of the conversion cycle,

8 μs, the part remains in auto shutdown mode. The AD7928 can

be said to dissipate 2.5 μW for the remaining 8 μs of the

conversion cycle. If the throughput rate is 100 kSPS, the cycle

time is 10 μs and the average power dissipated during each cycle is

(2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW

Figure 25 shows the maximum power vs. throughput rate when

using the auto shutdown mode with 3 V and 5 V supplies.

AVDD = 5V

AVDD = 3V

0.1

0.01

100

150

200

250

300

350

THROUGHPUT (kSPS)

Figure 25. AD7928 Power vs. Throughput Rate

SERIAL INTERFACE

Figure 27, Figure 28, and Figure 29 show the detailed timing

diagrams for serial interfacing to the AD7908, AD7918, and

AD7928, respectively. The serial clock provides the conversion

clock and also controls the transfer of information to and from

the AD7908/AD7918/AD7928 during each conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode,

takes the bus out of three-state; the analog input is sampled at

this point. The conversion is also initiated at this point and

requires 16 SCLK cycles to complete. The track-and-hold goes

back into track on the 14th SCLK falling edge as shown in

Figure 27, Figure 28, and Figure 29 at Point B, except when the

write is to the SHADOW register, in which case the track-and-

hold does not return to track until the rising edge of CS, that is,

Point C in Figure 30. On the 16th SCLK falling edge, the DOUT

line goes back into three-state. If the rising edge of CS occurs

before 16 SCLKs have elapsed, the conversion is terminated, the

DOUT line goes back into three-state, and the control register is

not updated; otherwise DOUT returns to three-state on the

16th SCLK falling edge as shown in Figure 27, Figure 28, and

Figure 29. Sixteen serial clock cycles are required to perform the

conversion process and to access data from the AD7908/

AD7918/AD7928. For the AD7908/AD7918/AD7928, the

8/10/12 bits of data are preceded by a leading zero and the

3-channel address bits (ADD2 to ADD0) identify which

channel the result corresponds to. CS going low provides the

leading zero to be read in by the microcontroller or DSP. The

three remaining address bits and data bits are then clocked out

by subsequent SCLK falling edges beginning with the first

address bit (ADD2). Thus the first falling clock edge on the

serial clock has a leading zero provided and also clocks out

Address Bit ADD2. The final bit in the data transfer is valid on

the 16th falling edge, having been clocked out on the previous

(15th) falling edge.

Writing of information to the control register takes place on the

first 12 falling edges of SCLK in a data transfer, assuming the

MSB, that is, the WRITE bit, has been set to 1. If the control

writing of information to the SHADOW register takes place on

all 16 SCLK falling edges in the next serial transfer, as shown for

example on the AD7928 in Figure 30. Two sequence options can

be programmed in the SHADOW register. If the user does not

want to program a second sequence, then the eight LSBs should

be filled with zeros. The SHADOW register is updated upon the

rising edge of CS and the track-and-hold begins to track the

first channel selected in the sequence.

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