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HC55151 Datasheet(PDF) 19 Page - Intersil Corporation |
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HC55151 Datasheet(HTML) 19 Page - Intersil Corporation |
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19 / 35 page ![]() 4-19 Digital Logic Inputs Table 1 is the logic truth table for the 3V to 5V logic input pins. A combination of the control pins C3, C2 and C1 select 1 of the possible 6 operating states. The 8th state listed is Thermal Shutdown. Thermal Shutdown protection is invoked if a fault condition on the tip or ring causes the junction temperature of the die to exceed 175oC. A description of each operating state and the control logic follows: Open Circuit State (C3 = 0, C2 = 0, C1 = 0) In this state, the tip and ring outputs are in a high impedance condition (>1M Ω). No supervisory functions are available and SHD and GKD outputs are at a TTL high level. 4-wire loopback testing can be performed in this state. With the PTG pin floating, the signal on the VTX output is 180 o out of phase and approximately 2 times the VRX input signal. If the PTG pin is grounded, then the amplitude will be approximately the same as its input and 180o out of phase. Ringing State (C3 = 0, C2 = 0, C1 = 1) In this state, the output of the ring relay driver pin (RRLY) goes low (energizing the ring relay to connect the ringing signal to the phone) if either of the following two conditions are satisfied: (1) The RSYNC_REV pin is grounded through a resistor - This connection enables the RRLY pin to go low the instant the ringing state is invoked, without any regard for the ringing voltage (90VRMS -120VRMS) across the relay contacts. The resistor (34.8k Ω to 70kΩ) is required to limit the current into the RSYNC_REV pin. (2) A ring sync pulse is applied to the RSYNC_REV pin - This connection enables the RRLY pin to go low at the command of a ring sync pulse. A ring sync pulse should go low at zero voltage crossing of the ring signal. This pulse should have a rise and fall time <400 µs and a minimum pulse width of 2ms. Zero ring current detection is performed automatically inside the SLIC. This feature de-energizes the ring relay slightly before zero current occurs to partially compensate for the delay in the opening of the relay. The SHD output will go low when the subscriber goes off hook. Once SHD is activated, an internal latch will prohibit the re-ringing of the line until the ringing code is removed and then reapplied. The state prior to ringing the phone, can not be the Reverse Active State. In the reverse active state the polarity of the voltage on the CRT_REV_LVM capacitor, will make it appear as if the subscriber is off hook. This subsequently will activate an internal latch prohibiting the ringing of the line. TABLE 1. DETECTOR STATES STATE C3 C2 C1 SLIC OPERATING STATE ACTIVE DETECTOR OUTPUT SHD GKD_ LVM 0 0 0 0 Open Circuit State 4 wire loopback test capability HIGH HIGH 1 0 0 1 Ringing State (Previous State cannot be Reverse Active State) Ring Trip Detector HIGH 2 0 1 0 Forward Active State Loop Current Detector Ground Key Detector 3 0 1 1 Test Active State Requires previous state to be in the Forward Active state to determine the On hook or Off hook status of the line. On Hook Loopback Detector LOW Ground Key Detector HIGH Off Hook Loop Current Detector LOW Line Voltage Detector 4 1 0 0 Tip Open - Ground Start State Ground Key Detector 5 1 0 1 Reserved Reserved N/A N/A 6 1 1 0 Reverse Active State Loop Current Detector Ground Key Detector 7 1 1 1 Test Reversal Active State Requires previous state to be in the Reverse Active state to determine the On hook or Off hook status of the line. On Hook Loop Current Detector HIGH Off Hook Loop Current Detector LOW Line Voltage Detector 8 X X X Thermal Shutdown LOW LOW HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151 |
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