High Frequency Divider/PLL Synthesizer

Data Sheet

ADF4007

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2004–2012 Analog Devices, Inc. All rights reserved.

FEATURES

7.5 GHz bandwidth

Maximum PFD frequency of 120 MHz

Divide ratios of 8, 16, 32, or 64

2.7 V to 3.3 V power supply

Separate charge pump supply (V

voltage in 3 V systems

R

Hardware power-down mode

APPLICATIONS

Satellite communications

Broadband wireless access

CATV

Instrumentation

Wireless LANs

GENERAL DESCRIPTION

The ADF4007 is a high frequency divider/PLL synthesizer that

can be used in a variety of communications applications. It can

operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.

It consists of a low noise digital PFD (phase frequency detector), a

precision charge pump, and a divider/prescaler. The divider/

prescaler value can be set by two external control pins to one of

four values (8, 16, 32, or 64). The reference divider is permanently

A complete PLL (phase-locked loop) can be implemented if the

synthesizer is used with an external loop filter and a VCO (voltage

controlled oscillator). Its very high bandwidth means that

frequency doublers can be eliminated in many high frequency

systems, simplifying system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

N2

N1

GND

R COUNTER

÷ 2

MUX

MUXOUT

CPGND

CP

PHASE

FREQUENCY

DETECTOR

REFERENCE

CHARGE

PUMP

ADF4007

N COUNTER

÷ 8, ÷ 16,

÷ 32, ÷ 64

M2

M1

Figure 1.