5

Pin Descriptions

PIN NO.

PIN NAME

TYPE

PIN DESCRIPTION

1

OUTEN

Input

Output enable high input signal used to command the regulator on and a low input signal turns

the regulator off.

2-7

VID[0:5]

Input

Voltage identification (6 bit). Programs Vout regulation voltage.

8, 21, 39, 57

VDD_CORE

Power

IC internal core supply voltage (1.8 VDC logic).

9

PWRGD

Output

Power Good high output signal to indicate the regulator output voltage is within the specified

range. A low signal indicates the voltage is not within range.

10, 25, 42,

44, 54

VDD_IO

Power

IC I/O input supply voltage (3.3 VDC logic).

11

MCLK

Output

EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is

clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs.

12

MDO

Output

13

MDI

Input

EEPROM external memory data input. Compliant with SPI EEPROMs.

14

MCS

Output

EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs.

15, 18, 22,

26, 30, 34

NDRIVE[1:6]

Output

Low side drive signal used to initiate the ISL6580 to turn on the LSFET.

16, 19, 23,

27, 31, 35

PWM[1:6]

Output

PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices.

17, 20, 24,

28, 32, 36

IDIG[1:6]

Input

Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The

remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580

P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.)

IDIG is an input that is received at SYSCLK/2, normally 66.6MHz.

29

EXT_Reset

Input

Voltage identification (6 bit). Programs Vout regulation voltage.

33, 48, 50,

51

TEST[1:4]

Output

Test pins for part evaluation

37, 38, 40,

41

NC

N/A

These pins have not been bonded out.

43

SYSCLK

Input/Output

System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the

internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency.

45

ERR

Input

Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into

the control loop and used to regulate the output voltage.

46

SOC

Input

Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal.

47

ATRL

Input

Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on

the converter output.

49

ATRH

Input

Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the

converter output.

52

SDATA

Input/Output

Controller serial interface for communication, monitoring, and configuration data between the

ISL6580 and ISL6590 controller.

53

SCLK

Output

Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the

Backside serial bus.

55

ATX

Output

Asynchronous Serial Interface Transmit

56

ARX

Input

Asynchronous Serial Interface Receive

58

OSC_OUT

Output

Only used if part is using a crystal to generate the system clock.

59

OSC_IN

Input

Requires a 33.33MHz oscillator or crystal which is used to generate system clock.

60

PLL_DIG_VSS

PLL Bypass

Ground

Input

Digital Ground for the 4X clock multiplier PLL

.

Test mode to bypass PLL input to core.

61

PLL_DIG_VDD

Power

1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic)

.

62

PLL_ANA_VSS

Ground

Analog Ground for the 4X clock multiplier PLL.

63

PLL_ANA_VDD

Power

1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic).

64

PLL_Filter

Analog Input

Filter cap for PLL.

65

GND

Ground

Paddle IC Ground

ISL6590