On-chip voltage regulator (VREG)

AN2871

12/25

Doc ID 15304 Rev 3

Example 1: SPC560P50, 64 MHz in motor control mode

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Power

Maximum steady state MCU current: 100 mA

Maximum collector voltage 5.0 V + 10% = 5.5 V

Minimum emitter voltage: = 1.15 V

Required power = (5.5 V

 1.15 V) * 0.1 = 435 mW

Proposed transistor: BCP68 in SOT223

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Temperature

Target system ambient = 125 °C

FR4 with thermal vias for SOT223 = 12 °C/W

Heatsink to ambient + 3 °C (depends upon power loading in target system)

Junction temperature = (125 °C + 3 °C) + (12 °C/W + 17 °C/W) * 0.442 W = 141 °C

Example 2: SPC560P50, 64 MHz in airbag mode

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Power

Maximum steady state MCU current: 66 mA

Maximum collector voltage 3.3 V + 10% = 3.6 V

Minimum emitter voltage: = 1.15 V

Required power = (3.6 V

 1.15 V) * 0.066 = 162 mW

Proposed transistor: BCP68 in SOT223

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Temperature

Target system ambient = 105 °C

FR4 with thermal vias for SOT223 = 12 °C/W

Heatsink to ambient + 3 °C (depends upon power loading in target system)

Junction temperature = (105 °C + 3 °C) + (12 °C/W + 17 °C/W) * 0.131 W = 112 °C

2.2

Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz

input clock. Furthermore, the FMPLL supports programmable frequency modulation of the

system clock.