Supply pins and decoupling

AN2871

20/25

Doc ID 15304 Rev 3

4.1.2

Specific supply decoupling

Although SPC560Pxx/SPC56APxx/SPC56APxx devices have only one external supply,

several types of pins are connected to this supply and consequently must have a specific

decoupling.

Flash, Oscillator

I/Os

I/O decoupling should be checked according to the I/O real activity.

with a value of 33 nF to 100 nF and the other one with a value of 470 pF to 1 nF.

ADC

During SPC560Pxx/SPC56APxx design, several supply schemes of the two ADCs have

been analyzed and simulated. The best one is the one with shared supply and reference per

ADC.

For this reason, serial resistance on ADC supply and GND must be avoided.

PLL

The PLL is supplied by the 1.2 volt rail. Recommended decoupling capacitors are 100 nF

and 10 nF.

Main supply decoupling

The recommendations described above assume that enough reservoir capacitors are

placed at the output of the VREG generating the 5 V or 3.3 V supply for the

SPC560Pxx/SPC56APxx device. Those capacitors are dependent on the type of voltage

regulator used and hence are not specified here.

4.1.3

Power-on current control

On power-on, the embedded voltage regulator starts to work at about 2.8 V and stops to at

about 2.5 V (0.3 V hysteresis with power-on threshold).

Once the minimum supply is met, the embedded voltage regulator then switches ON the

external ballast.

Slope characteristics on all VDD during power up has to be inside TVDD parameter range