AN2871

Supply pins and decoupling

Doc ID 15304 Rev 3

19/25

In order to remain in the range requested by DS, required capacitor values have to include

the de-rating factor coming from tolerance, temperature, and aging effects. These factors

must be taken into account to assure proper operation under worst case conditions.

X7R type materials are recommended for all capacitors, based also on ESR characteristics.

In Figure 7 is shown as example the decoupling of 1.2 V rail for SPC50P50L5 whose

number of supply pins VDD_LV_CORx/VSS_LV_CORx is 4. It can be avoided to use

decoupling cap near pin pair VDD_LV_REGCOR/VSS_LV_REGCOR.

Figure 7.

Decoupling of 1.2 V rail

Layout recommendations:

●

ballast output.

●

Use preferably a small plane to distribute Vcore (that is, 1.2 V) with a low parasitic

inductance to each pin or a star topology from the ballast output.

●

The Resulting parasitic inductance, ESL of VDD_HV_REG, BCTRL and

described in the device datasheet

●

Low Equivalent Series Resistance (ESR) and low Equivalent Series Inductance (ESL)

capacitors should be used for the 10 µF stability capacitors. Use preferably ceramic

capacitors. Do not use electrolytic capacitors as stabilization capacitors.

Note:

Note:

The use a multi-layer printed circuit board (PCB) with a separate layer dedicated to the

ground and another one to the voltages supply is recommended.