Halt (HT) bit

AN3060

16/23

Doc ID 16253 Rev 2

Figure 9.

Clock and non-clock registers

Coherency

The clock counters are buffered to ensure coherency. At the start of a read of the clock

registers, the device will copy the counters to the buffer/transfer registers, then make no

further updates to these registers for the duration of the read cycle. (The HT bit is not set at

this time, but the updates are halted.) By copying all the counters simultaneously, the values

in the registers will all be from the same instant in time and thus will be coherent.

Example of incoherency

Without having the intervening buffer/transfer registers, if the user began directly reading the

counters at 23:59:59, a read of the seconds register would return 59 seconds. After the

address pointer incremented, the next read would return 59 minutes. The next read should

return 23 hours, but if the clock happened to increment between the reads, the user would

see 00 hours. When the time was re-assembled, it would appear as 00:59:59, and thus be

off by one hour. It would be incoherent.

By using the buffer/transfer registers to hold a copy of the time, the user is able to read the

entire set of registers without any values changing during the read.

Similarly, when the application needs to change the time in the counters, it is necessary that

all the counters be loaded simultaneously. Thus, the user writes sequentially to the various

buffer/transfer registers, then they are copied to the counters in a single transfer thereby

coherently loading the counters.

32KHz

OSC

DIVIDE BY

32768

1 Hz

READ / WRITE

BUFFER

TRANSFER

REGISTERS

SERIAL

SERIAL BUS

TRANSFER

REGISTER

CENTURIES

YEARS

MONTHS

DATE

DAY-OF-WEEK

WATCHDOG

HOURS

MINUTES

SECONDS

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

COUNTER

NON-CLOCK

REGISTERS

SQUAREWAVE

CALIBRATION

CLOCK COUNTERS

ARE BUFFERED VIA

BUFFER/TRANSFER

REGISTERS

NON-CLOCK REGISTERS

ARE DIRECTLY ACCESSED

WRITE FLAG

HALT BIT

WRITES TO ANY

CLOCK REGISTER CAUSE

WRITE FLAG TO BE SET.

AT END OF WRITE CYCLE,

IF WRITE FLAG IS SET,

BUFFER/TRANSFER

REGISTERS COPIED TO

COUNTERS

AM04727v1