AN3060

Halt (HT) bit

Doc ID 16253 Rev 2

17/23

Write flag

The copying to the counters is caused by an internal write flag which gets set anytime a

write occurs in one of the buffer transfer registers, but not to any of the other (non-clock)

registers. For example, writing the watchdog or calibration register will not set the write flag,

but writing the seconds or day-of-week will set the flag.

sees the write flag set, it copies all the buffer transfer registers to the clock counters. Even if

only one or two of the buffer/transfer registers is over-written by the application, all the

registers will be copied to the counters.

Auto-setting of the HT bit

Whenever the device is powered down, the time and date are copied to the buffer/transfer

registers and the HT bit is set automatically. At power-up, the user can read the device (with

the HT bit still set) and retrieve the time of power-down from the registers. This allows the

application to determine how long the power outage lasted which is needed in some

situations. As long as the HT bit remains set, reads will return the time of power-down

(assuming no writes have occurred to alter the contents of the buffer/transfer registers).

In order to read the present time, the user must first clear (write a 0 to) the HT bit.

Subsequent reads will return the current time. Subtracting the time of power-down from the

present time establishes the length of the power outage.

Writing with the HT bit set

Following a power failure, the buffer/transfer registers contain the time of power-down.

Should the user write to any of the clock registers (addresses 0x00 to 0x07 in the table

above), the write flag will be set. Thus, at the end of the write cycle, the counters will be

updated from the registers.

If the HT bit is still set, the buffer/transfer registers contain the time of power-down modified

by the written value. Thus, at the end of the write sequence, the modified time of power-

down will be written back into the counters thus causing an apparent loss of time.

Example: Let the time/date of power down be, Mon, 9-Mar-08, 7:23:44pm. At power-up,

prior to clearing the HT bit, the user writes the ST bit in the seconds register thus setting the

write flag, but writes no other bits. At the end of the write cycle, the present time will revert

to the time of power-down thus resulting in an apparent loss of time.

Conversely, if the HT bit had been cleared prior to the write, the buffer/transfer registers

would have been updated to the present time. As before, a write of the ST bit would have

set the write flag, but the resultant update of the counters would have placed the current

time back in them. They would have been written over with the same values already present

in the counters. No loss of time would occur.

For more information, refer to application note AN1572.