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AN4266 Datasheet(PDF) 53 Page - STMicroelectronics

Part # AN4266
Description  Safety application guide for SPC56xL70xx family
PDF  76 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4266 Datasheet(HTML) 53 Page - STMicroelectronics

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AN4266
Functional safety requirements for application software
Doc ID 024283 Rev 2
53/76
Figure 16.
Logic scheme of the LVD_FLASH, LVD_GPIO and LVD_VREG
Operation of the LVD_FLASH, LVD_GPIO and LVD_VREG is as follows (software
intervention is not needed):
●
A single LVD (PMU LVD or module LVF) can trigger a fault even if the other LVD is
faulty (this event signals the MC_RGM)
●
During each power on cycle self-test circuitry is able to detect failures on one of the two
LVD’s (this event signals the FCCU).
Mandatory: Core voltage LVD and HVD implement a hardware assisted self-test that needs
to be initiated by software once after the boot.
Note:
Rationale: To check the integrity of the LVD and HVD
Note:
Implementation hint: The hardware assisted self-tests are initiated by configuring
PMUCTRL_CTRL[SILHT[1:0]].
If the self-test passes, an NCF is triggered. If the self-test fails, a PMUCTRL_IRQS flag and
CF are asserted.
Apart from the self-test, the use of the power management unit for ASIL D applications is
transparent to the user, because the operation of the PMU is automatic. The SPC56xL70xx
embeds three LVDs which can detect a failure in the 3.3V power supply. Considering the
failure mode “Wrong Power Regulation”, a diagnostic coverage of 90% is estimated against
both a soft error and DC fault.
3.24
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) provides hardware access control for all memory
references generated in a device. Using pre-programmed region descriptors that define
memory spaces and their associated access rights, the MPU concurrently monitors all
system bus transactions (including those initiated by the eDMA or FlexRay controller) and
evaluates the appropriateness of each transfer.
Note: This scheme represents only the logical configuration and not the actual silicon
implementation structure.
PMU LVD
module LVD
self-test
circuitry
reference
voltage 2
3.3 V supply
to MC_RGM
(destructive reset)
to FCCU



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