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UPD178024GC Datasheet(PDF) 1 Page - NEC

Part # UPD178024GC
Description  8-BIT SINGLE-CHIP MICROCONTROLLER
PDF  56 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD178024GC Datasheet(HTML) 1 Page - NEC

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©
1999
DATA SHEET
DESCRIPTION
The
µPD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning
systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit.
In addition, three serial interfaces, I2C bus (IIC0), three-wire (SIO3), and UART are provided.
Moreover, a flash memory model, the
µPD178F124, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178024, 178124 Subseries User’s Manual : U13915E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
• High-capacity ROM and RAM
Item
Program Memory (ROM)
Data Memory
Part Number
Internal high-speed RAM
µPD178023
24K bytes
1024 bytes
µPD178024
32K bytes
MOS INTEGRATED CIRCUIT
µPD178023,178024
Document No. U14126EJ1V0DS00 (1st edition)
Date Published September 1999 N CP(K)
Printed in Japan
8-BIT SINGLE-CHIP MICROCONTROLLER
• Instruction cycle:
0.45/0.89/1.78/3.56/7.11
µs (with crystal resonator of
fX = 4.5 MHz)
• Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (I2C bus and UART mode), timers, frequency
counter, power-ON clear circuit
• Hardware for PLL frequency synthesizer
Dual modulus prescaler, programmable divider,
phase comparator, charge pump
• Vectored interrupt sources: 17
• Supply voltage
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.


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