UPD178024GC datasheet(12/56 Pages) NEC

12 / 56 page

µPD178023, 178024

Data Sheet U14126EJ1V0DS00

1.2 Pins Other Than Port Pins

Pin Name

I/O

Function

At Reset

Shared by:

INTP0-INTP4

Input

External maskable interrupt input whose valid edge

Input

P00-P04

(rising edge, falling edge, or both rising and falling edges)

can be specified.

SI3

Input

Serial data input to serial interface.

Input

P70

SO3

Output

Serial data output from serial interface.

Input

P71

SDA0

I/O

Serial data input/output to/from

N-ch open drain I/O

Input

P76

serial interface.

SCK3

I/O

Serial clock input/output to/from serial interface.

Input

P72

SCL0

N-ch open drain I/O

P77

RXD0

Input

Serial data input to asynchronous serial interface (UART0).

Input

P74

TXD0

Output

Serial data output from asynchronous serial interface (UART0).

P75

TI50

Input

External count clock input to 8-bit timer (TM50).

Input

P33

TI51

External count clock input to 8-bit timer (TM51).

P34

TO50

Output

8-bit timer (TM50) output.

Low-level

P130

TO51

8-bit timer (TM51) output.

output

P131

BEEP0

Output

Buzzer output.

Input

P36

ANI0-ANI5

Input

Analog input to A/D converter.

Input

P10-P15

EO0, EO1

Output

Error out output from charge pump of PLL frequency

–

synthesizer.

VCOL

Input

Inputs local oscillation frequency of PLL (in HF and MF modes).

–

VCOH

Inputs local oscillation frequency of PLL (in VHF mode).

AMIFC

Input

Input to AM intermediate frequency counter.

Input

–

FMIFC

Input to FM or AM intermediate frequency counter.

RESET

Input

System reset input.

–

Input

Connection of crystal resonator for system clock oscillation.

–

––

REGOSC

–

Regulator for oscillator. Connect this pin to GND via 0.1-

µF–

–

capacitor.

REGCPU

–

Regulator for CPU power supply. Connect this pin to GND

–

via 0.1-

µF capacitor.

VDD

–

Positive power supply.

–

GND

–

Ground.

–

VDDPORT

–

Port power supply.

–

GNDPORT

–

Port ground.

–

VDDPLLNote

–

PLL positive power supply.

–

GNDPLLNote

–

PLL ground.

–

Internally connected. Directly connect this pin to GND.

–

Note

Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.

UPD178024GC Datasheet(PDF) 12 Page - NEC

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