Electronic Components Datasheet Search
  English  ▼

X  

AN4506 Datasheet(PDF) 12 Page - STMicroelectronics

Part # AN4506
Description  This document is intended to provide information
PDF  47 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4506 Datasheet(HTML) 12 Page - STMicroelectronics

Back Button AN4506 Datasheet HTML 8Page - STMicroelectronics AN4506 Datasheet HTML 9Page - STMicroelectronics AN4506 Datasheet HTML 10Page - STMicroelectronics AN4506 Datasheet HTML 11Page - STMicroelectronics AN4506 Datasheet HTML 12Page - STMicroelectronics AN4506 Datasheet HTML 13Page - STMicroelectronics AN4506 Datasheet HTML 14Page - STMicroelectronics AN4506 Datasheet HTML 15Page - STMicroelectronics AN4506 Datasheet HTML 16Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 47 page
background image
Reading angular rate data
AN4506
12/47
DocID026442 Rev 2
3.2
Using the status register
The device is provided with a STATUS register which should be polled to check when a new
set of data is available. The reading procedure should be the following:
The check performed at step 3 allows the user to understand whether the reading rate is
adequate compared to the data production rate. If one or more angular rate samples have
been overwritten by new data, because of an insufficient reading rate, the ZYXOR bit of the
STATUS register is set to 1.
The overrun bits and the new data available bits are automatically cleared when all the data
present inside the device have been read and new data have not been produced in the
meantime.
3.3
Using the data-ready (DRDY) signal
The device may be configured to have one HW signal to determine when a new set of
measurement data is available for reading. This signal is represented by the XYZDA bit of
the STATUS register. The signal can be driven to the DRDY/INT2 pin by setting the
I2_DRDY bit to 1 in the CTRL3 register and its polarity to active-low or active-high through
the H_Lactive bit of the CTRL3 register (see Section 5.1).
The data-ready signal rises to 1 when a new set of angular rate data has been generated
and is available for reading. The interrupt is reset when the higher part of one of the enabled
channels has been read (29h, 2Bh, 2Dh).
1.
Read STATUS
2.
If STATUS(3) = 0 then go to 1
3.
If STATUS(7) = 1 then some data have been overwritten
4.
Read OUT_X_L
5.
Read OUT_X_H
6.
Read OUT_Y_L
7.
Read OUT_Y_H
8.
Read OUT_Z_L
9.
Read OUT_Z_H
10. Data processing
11. Go to 1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com