AN3994 datasheet(40/53 Pages) STMICROELECTRONICS

40 / 53 page

MOSFET critical parameters in high switching environments

AN3994

40/53

Doc ID 022380 Rev 1

Figure 47.

Gate driving and main switching loops for a MOSFET in a BOOST-like

topology

A simple clamped inductive load circuit test was adopted to evaluate the differences

between two layout configurations and their respective effect on the switch performance. It's

important to remark that all layout options described in the following sections have been

implemented on the same test circuit.

All tests have been carried on the STW77N65M5, as the advantage offered by the layout

optimization and the 4-pin solution (which is described shortly) is as important as high

current levels are involved.

In the first layout configuration, the common source path between the main switching loop

and the driving loop is a few cm long, while in the second layout configuration, the common

source path has been shortened to the length of the source pin. In both cases, the drain

parasitic loop inductance has been neglected thanks to a very short distance between the

bus capacitors and the switch. The following curves show the Eon and the Eoff energies of

STW77N65M5 which were issued with the same RG, gate driving signal (0 V to 10 V), and

VDD=400 V conditions.

AN3994 Datasheet(PDF) 40 Page - STMicroelectronics