UPD63 datasheet(50/68 Pages) NEC

50 / 68 page

µPD63, 63A, 64

AC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Command execution time

tCY

VDD = 2.2 to 3.6 V

7.9

µs

15.9

µs

KI, S0, S1 high-level width

µs

When releasing

at HALT mode

µs

STANDBY mode

at STOP mode

Note

µs

RESET low-level width

tRSL

µs

Note 10 + 52/fX + oscillation growth time

Remark tCY = 64/fX (fX: System clock oscillator frequency)

POC Circuit (mask optionNote 1) (TA = –20 to +70 ˚C)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

POC-detected voltageNote 2

VPOC

0.9

1.6

2.2

POC circuit current

IPOC

0.9

1.0

µA

Notes 1. Operates effectively under the conditions of TA = –20 to +70 ˚C, VDD = 2.2 to 3.6 V, and fX = 2.4 to

4 MHz.

2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal

reset is released.

From the time of VPOC

≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the

period of VPOC

≥ VDD lasts less than 1 ms, the internal reset may not take effect.

UPD63 Datasheet(PDF) 50 Page - NEC

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