UPD63 datasheet(17/68 Pages) NEC

17 / 68 page

µPD63, 63A, 64

3.3 Control Register 0 (P3)

Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.

When reset, the register becomes 0000 0011B.

Table 3-4. Control Register 0 (P3)

Bit

Name

—

DP (Data pointer) TCTL

CARY

MOD1

MOD0

DP9

DP8

Set

Fixed

1/1

Refer to Table 3-5.

value

to “0”

1/2

OFF

When reset

00000011

b0, b1 : These bits specify the carrier frequency and duty ratio of the REM output.

: This bit specifies the availability of the carrier of the frequency specified by b0 and b1.

“0” = ON (with carrier); “1” = OFF (without carrier; high level)

: This bit changes the carrier frequency and the timer clock’s frequency division ratio.

“0” = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: fX/64)

“1” = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/128)

Table 3-5. Timer Clock and Carrier Frequency Setup

Timer Clock

Carrier Frequency (Duty Ratio)

0000fX/64

fX/8 (Duty 1/2)

fX/64 (Duty 1/2)

fX/96 (Duty 1/2)

fX/96 (Duty 1/3)

××

Without carrier (high level)

0000fX/128

fX/16 (Duty 1/2)

fX/128 (Duty 1/2)

fX/192 (Duty 1/2)

fX/192 (Duty 1/3)

××

Without carrier (high level)

b4 and b5

: These bits specify the high-order 2 bits (DP8 and DP9) of ROM’s data pointer.

Remark

×: don’t care

UPD63 Datasheet(PDF) 17 Page - NEC

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