AN2169

New functionalities

17/33

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XIR0SEL = 0x0100, only CAN1 interrupt is enabled and will generate an interrupt to the

ST10 through XP0IC

●

XIR2SEL = 0x0, not used

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XIR3SEL = 0x2000, only PLL unlock interrupt is enabled and will generate an interrupt to

the ST10 through XP3IC.

Then, in the interrupt routines associated to the XPxIC, the respective flag in XIRxSEL register

must be cleared. Since the XIRxSEL registers are not bit addressable, a pair of registers (a pair

for each XIRxSEL) is provided to allow setting and clearing the bits of XIRxSEL without risking

to overwrite requests coming after reading the register and before writing it. Therefore the

following registers must be written to clear the flags:

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in the CAN1 interrupt routine, XIR0CLR (@ EB14h) = 0x0001

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in the PLL unlock interrupt routine, XIR3CLR (@ EB44h) = 0x0020

Additional information on the X-Interrupt multiplexer structure

Figure 2 shows that the X-Interrupt sources are connected to the interrupt request flag of the

XIRxSEL registers and to the XPxIR request flag via an AND gate with the enable bit. This AND

gate is activated by a transition on the Interrupt source line and not by the latched value in the

XIRxSEL register meaning:

●

A transition on the IT source line will generate an interrupt to the ST10 core if the source is

enabled.

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Writing to an interrupt request flag in a XIRxSEL register will not generate an interrupt to

the ST10 core.

Example: If XIR0SEL = 0x0100: CAN1 interrupt enabled on XP0IC interrupt

To trigger by software the CAN1 interrupt routine with XP0IC register, the following code must

be used:

XIR0SET = 0x0001;/* Set CAN1 interrupt request Flag in XIR0SEL

register */

XP0IC = XP0IC | 0x0080;/* Set XP0IR flag and generate an interrupt

routine to the ST10 */

Executing only the first line will only set the flag in the XIR0SEL register but will not be seen by

the AND gate and can not set the XP0IR flag.

2.6

Programmable divider on CLKOUT

A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT

signal (P3.15).

XCLKOUTDIV (E902h)

XBUS

Reset Value: --00h

15

14

13

12

11

10

987654

3210

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DIV

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