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AN2169 Datasheet(PDF) 24 Page - STMicroelectronics |
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AN2169 Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 33 page ![]() New registers AN2169 24/33 4.1.1 Hardware impact None. 4.1.2 Software impact The value has to be changed from its default reset one to match XRAM size compatibility. Refer to XRAM section for more details. 4.2 XPEREMU register This register has been added as a write-only register. ST10F276: XPEREMU (EB7Eh) XREG Reset Value: XXXXh The bit description is exactly the same as XPERCON. 4.2.1 Hardware Impact None. 4 RTCEN: RTC Enable Bit 0: Accesses to the on-chip Real Time Clock are disabled, external access performed. 1: The on-chip Real Time Clock is enabled and can be accessed. 3 XRAM2EN: XRAM2 Enable Bit 0: Accesses to the on-chip XRAM2 block are disabled, external access performed. 1: The on-chip XRAM2 is enabled and can be accessed. 2 XRAM1EN: XRAM1 Enable Bit 0: Accesses to the on-chip XRAM1 block are disabled, external access performed. 1: The on-chip XRAM1 is enabled and can be accessed. 1 CAN2EN: CAN2 Enable Bit 0: Accesses to the CAN2 XPeripheral and its functions are disabled (P4.4 and P4.7 pins can be used as general purpose IOs) 1: The CAN2 X-Peripheral is enabled and can be accessed. 0 CAN1EN: CAN1 Enable Bit 0: Accesses to the CAN1 XPeripheral and its functions are disabled (P4.5 and P4.6 pins can be used as general purpose IOs) 1: The CAN1 X-Peripheral is enabled and can be accessed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - --- - XMISC EN XI2C EN XSSC EN XASC EN XPWM EN XFLASH EN XRTC EN XRAM2 EN XRAM1 EN CAN2 EN CAN1 EN - --- - W W W W W W W W W W W Bit Function |
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