AN2867 datasheet(17/41 Pages) STMICROELECTRONICS

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AN2867

Pierce oscillator design

Note:

If RExt is too low, there is no power dissipation in the crystal. If RExt is too high, there is no

oscillation: the oscillation condition is not reached.

3.6

Startup time

The startup time is the time required by the oscillation to start up and then build up until it

reaches a stable oscillation phase. The startup time depends, among other factors, on the

Q-factor of the resonator used. If the oscillator is paired with a quartz-crystal resonator

characterized by its high Q-factor then the startup time will be higher if a ceramic resonator

is used (ceramic resonators are know for their poor Q-factor compared to quartz-crystal

resonators). The startup time also depends on the external components, CL1 and CL2, and

on the crystal frequency. The higher the crystal nominal frequency, the lower the start up

time. In addition the startup problems are usually due to the fact that the gain margin is not

properly dimensioned (as explained previously). This is caused either by CL1 and CL2 being

too small or too large, or by the ESR being too high.

As an example, an oscillator paired with a few-MHz nominal frequency crystal resonator

would typically start up after a delay of few ms.

The startup time of a 32.768 kHz crystal ranges from 1 to 5 s.

3.7

Crystal pullability

Crystal pullabilty, also known as crystal sensitivity, measures the impact of small variations

of the load capacitance seen by the crystal on the oscillation frequency shifting. This

parameter usually has more importance when dealing with low-speed oscillators, since they

are used to clock time-keeping functions (such as real-time clock functions).

When the final application is still in design stage, the influence of this parameter on the low-

speed oscillator accuracy (and consequently on all the time-keeping functions clocked by

this oscillator) is not so obvious. This is due to the fact that the designer fine tunes the load

capacitors until the desired oscillation frequency is obtained. When the design reaches

production stage. it is frozen and all the passive components including the load capacitors

have their values well defined. Any change of the load capacitance will directly induce a shift

of the oscillation frequency. Changes in the capacitive load (CL) seen by the crystal may be

thought of as due to inadequate operation environment and only happening when the final

design is not properly operated. In practice, this is not true since changes of the load

capacitance are rather frequent and must by taken into account by the designer. The main

contributors to the capacitive load (CL) seen by the oscillator are the following:

•

The capacitance of the load capacitors CL1 and CL2

•

The stray capacitance of the PCB paths

•

The parasitic capacitance of the oscillator pins.

Any change on the capacitances listed above directly shifts the oscillation frequency. When

the design is in production stage, many of these capacitance values cannot be accurately

controlled. Selecting a crystal with low-pullability will limit the influence of such production

uncertainties on the final oscillation frequency accuracy.

Generally speaking, the higher the load capacitance (CL) of a crystal, the lower its pullability.

As an example, let us consider a crystal with a pullability of 45 PPM/pF. To fine tune the

oscillation frequency, this crystal is loaded by two C0G ceramic capacitors, CL1 and CL2,

with equal capacitances equal to 7 pF. C0G ceramic capacitors have a tolerance value of

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