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LT3487

3487f

PI FU CTIO S

CAP (Pin 1): Disconnect-PNP Emitter and Positive Schottky

Cathode. Acts as an intermediate positive (boost) output.

Connect boost output capacitor to this pin.

SWP (Pin 2): Switch Pin and Schottky Anode for Positive

Channel. Connect boost inductor to this pin.

VBAT (Pin 3): Battery Voltage. Connect this pin to the sup-

ply voltage for the boost inductor. The disconnect drive

current is returned to this pin. The disconnect operates

until CAP falls to 1.2V above VBAT.

SWN (Pin 4): Switch Pin for Negative (Inverter) Chan-

nel. Connect inverter input inductor and ﬂying capacitor

here.

DN (Pin 5): Anode of Internal Schottky for Inverter. Connect

inverter output inductor and ﬂying capacitor here.

VIN (Pin 6): Input Supply Pin. VIN is used to power the

control circuitry of the LT3487. This pin must be locally

bypassed with an X5R or X7R type ceramic capacitor.

FBN (Pin 7): Feedback Pin for Inverter. Connect feedback

resistor R2 from this pin to VNEG. Choose R2 according

to:

µA

NEG

= –

Pin voltage = 0V when regulated.

RUN/SS (Pin 8): Run/Soft-Start Pin. Connect to an open-

drain transistor. The transistor must sink 1.4µA from

RUN/SS. Pull RUN/SS below 100mV to shut down the chip.

Connect a capacitor from RUN/SS to ground to program

soft-start functionality. The soft-start will slowly bring the

boost channel into regulation and then slowly bring up

the inverter. RUN/SS must be above 1.6V to allow both

channels to reach full current. If soft-start is not required,

this pin can be driven with a logic signal, but the RUN/SS

voltage must remain below VIN.

FBP (Pin 9): Feedback Pin for Boost. Connect boost

feedback resistor R1 from FBP to CAP. Choose R1 ac-

cording to:

µA

POS

123

–.

Pin voltage = 1.23V when regulated.

VPOS (Pin 10): Output Pin for Boost Channel. VPOS is

the collector of the output disconnect PNP. Connect the

boost load to VPOS. Connect capacitor C5 between CAP

and VPOS for stability.

Exposed Pad (Pin 11): GND. Tie directly to ground plane

through multiple vias under the package for optimum

thermal performance.

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