UPD7225 datasheet(17/52 Pages) NEC

17 / 52 page

Data Sheet S14308EJ6V0DS00

µµµµPD7225

2.6 Blinking Data Memory

The blinking data memory stores blinking data used to control display on/off operation (blinking).

Blinking

operation can be performed in segment units. Each bit in blinking data memory corresponds to a bit in the data

memory; if a bit in the blinking data memory is set to 1, the corresponding segment will blink.

The blinking data memory is addressed by the data pointer at the same time the data memory is addressed. Data

is written by using the WRITE BLINKING DATA MEMORY command, and bit manipulation can be performed by

using the AND BLINKING DATA MEMORY, or OR BLINKING DATA MEMORY command.

The BLINKING ON

command is used to initiate blinking operation or select the blinking interval (refer to 3.2

Blinking Frequency

Setting)

2.7 Display Data Latch

The display data latch stores the data of the 32

× 4-bit segment driver. Each bit of the display data latch

corresponds to a bit in the data memory. All contents of the data memory are transferred to the display data latch at

the rising edge of /CS, and the contents displayed on the LCD are modified. If blinking is set, the contents of data

memory are modified by the contents of blinking data memory and the resulting values are transferred to the display

data latch.

The display data written to the display data latch is successively selected by the control function performed by the

LCD timing control, and converted to segment drive signal before output.

2.8 LCD Driver

The LCD driver consists of the segment driver and the common driver, and generates the segment drive signal

and common drive signal.

The segment driver outputs a segment signal so that the relationship with the common drive signal is select level if

the drive data stored in the display data latch is 1. If the drive data stored in the display data latch is 0, the output of

the segment driver will be non-select level.

The common drive signal sequentially drives the LCD common poles according to the time divison specificaion.

2.9 LCD Timing Control

The LCD timing control generates the LCD drive timing according to the number of time divisions, the frequency

division ratio, and bias method, and supplies it to the LCD driver. In addition, the LCD timing control outputs a /SYNC

signal from the /SYNC pin in order to synchronize the display timing of each

µPD7225 when configured in a multi-

chip configuration.

In a multi-chip configuration, the common signal can be used in common or blinking operation can be

synchronized by making a wired-OR connection with the /SYNC pin of each

µPD7225.

UPD7225 Datasheet(PDF) 17 Page - NEC