LTC3533 datasheet(7/16 Pages) LINER

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LTC3533

3533f

BLOCK DIAGRAM

–

PWM

LOGIC

AND

OUTPUT

PHASING

GATE

DRIVERS

AND

ANTI-CROSS

CONDUCTION

GND

UVLO

4.5A

1.6V

OSC

SUPPLY

CURRENT

LIMIT

SW A

SW1

VIN

1.8V TO 5.5V

SW2

SW D

ERROR

AMP

CLAMP

1.22V

ISENSE

AMP

REVERSE

CURRENT

LIMIT

SW B

RUN

SLEEP

SW C

VOUT

RUN/SS

RSS

CSS

VIN

BURST

0 = BURST MODE

1 = FIXED FREQUENCY

3533 BD

PWM

COMPARATORS

BURST MODE

OPERATION

CONTROL

–0.5A

OPERATION

The LTC3533 provides high efﬁciency, low noise power

for a wide variety of handheld electronic devices. The LTC

proprietary topology allows input voltages above, below

or equal to the output voltage by properly phasing the

output switches. The error ampliﬁer output voltage on VC

determines the output duty cycle of the switches. Since

VC is a ﬁltered signal, it provides rejection of frequencies

well below the switching frequency. The low RDS(ON), low

gate charge synchronous switches provide high frequency

pulse width modulation control at high efﬁciency. High

efﬁciency is achieved at light loads when Burst Mode

operation is entered and the LTC3533’s quiescent current

drops to a low 40µA.

LOW NOISE FIXED FREQUENCY OPERATION

Oscillator

The frequency of operation is programmed by an external

resistor from RT to ground, according to the following

equation:

f(kHz) = 33,170/RT(k)

LTC3533 Datasheet(PDF) 7 Page - Linear Technology

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