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LTC3533

3533f

OPERATION

Error Ampliﬁer

The error ampliﬁer is a voltage mode ampliﬁer. The loop

compensation components are conﬁgured around the

ampliﬁer (from FB to VC) to obtain stability of the converter.

For improved bandwidth, an additional RC feed-forward

network can be placed across the upper feedback divider

resistor. The voltage on the RUN/SS pin clamps the error

ampliﬁer output, VC, to provide a soft-start function.

Supply Current Limits

There are two different supply current limit circuits in the

LTC3533, working consecutively, each having internally

ﬁxed thresholds which vary inversely with VIN.

The ﬁrst circuit is a current limit ampliﬁer, sourcing cur-

rent into FB to drop the output voltage, should the peak

input current exceed 4.5A typical. This method provides a

closed loop means of clamping the input current. During

conditions where VOUT is near ground, such as during a

short circuit or startup, this threshold is cut to 750mA,

providing a fold-back feature. For this current limit feature

to be most effective, the Thevenin resistance from FB to

ground should be greater than 100k.

Should the peak input current exceed 7A typical, the second

circuit, a high speed peak current limit comparator, shuts

off PMOS switch A. The delay to output of this comparator

is typically 50ns.

Reverse Current Limit

During ﬁxed frequency operation, the LTC3533 operates in

forced continuous conduction mode. The reverse current

limit comparator monitors the inductor current from the

output through switch D. Should this negative inductor

current exceed 500mA typical, the LTC3533 shuts off

switch D.

Four-Switch Control

Figure 1 shows a simpliﬁed diagram of how the four in-

ternal switches are connected to the inductor, VIN, VOUT

and GND.Figure 2 shows the regions of operation for the

LTC3533 as a function of the control voltage, VC.

Dependent on VC’s magnitude, the LTC3533 will operate

in either buck, buck/boost or boost mode. The four power

switches are properly phased so the transfer between op-

erating modes is continuous, smooth and transparent to

the user. When VIN approaches VOUT the buck/boost region

is entered, where the conduction time of the four switch

region is typically 150ns. Referring to Figures 1 and 2, the

various regions of operation will now be described.

Buck Region (VIN > VOUT)

Switch D is always on and switch C is always off during

this mode. When the control voltage, VC, is above volt-

age V1, switch A begins to switch. During the off time of

switch A, synchronous switch B turns on for the remainder

of the period. Switches A and B will alternate similar to a

typical synchronous buck regulator. As the control volt-

age increases, the duty cycle of switch A increases until

the maximum duty cycle of the converter in buck mode

reaches DMAX_BUCK, given by:

DMAX_BUCK = 100 – D4SW %

where D4SW = duty cycle % of the four switch range.

SW1

SW2

PMOS A

NMOS B

PVIN

PMOS D

NMOS C

3533 F01

PVOUT

85%

DMAX

BOOST

DMIN

BOOST

DMAX

BUCK

DUTY

CYCLE

V4 (

≈1.5V)

V3 (

≈1.15V)

BOOST REGION

BUCK REGION

BUCK/BOOST REGION

V2 (

≈1V)

V1 (

≈0.7V)

3533 F02

A ON, B OFF

PWM CD SWITCHES

D ON, C OFF

PWM AB SWITCHES

FOUR SWITCH PWM

CONTROL

VOLTAGE, VC

Figure 1. Simpliﬁed Diagram of Output Switches

Figure 2. Switch Control vs Control Voltage, VC

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