Specifications ispLSI 2128VL

7

ispLSI 2128VL Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

Reg 4 PT Bypass

20 PT

XOR Delays

Control

PTs

I/O Pin

(Input)

Y0,1,2

GRP

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Delay

I/O Cell

ORP

GLB

GRP

I/O Cell

#24

#25, 26, 27

#33, 34,

35

#43, 44

#36

Reset

Ded. In

#21

#20

#28

#29, 30,

31, 32

#38,

39

GOE 0

#42

#40, 41

0491/2032

#22

Comb 4 PT Bypass #23

#37

#45

Derivations of

=

=

=

=

4.0ns

Logic + Reg su - Clock (min)

(

(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

(0.4 + 1.1 + 4.0) + (1.2) - (0.4 + 1.1 + 1.2)

=

=

=

=

Clock (max) + Reg h - Logic

(

(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

(0.4 + 1.1 + 4.2) + (2.8) - (0.4 + 1.1 + 4.0)

=

=

=

=

Note: Calculations are based upon timing specifications for the ispLSI 2128VL-150L.

Clock (max) + Reg co + Output

(

(#20 + #22 + #35) + (#31) + (#36 + #38)

(0.4 + 1.1 + 4.2) + (0.3) + (1.4 + 1.6)

Table 2-0042/2128VL

3.0ns

9.0ns