ispLSI

®

2128VL

2.5V In-System Programmable

SuperFAST™ High Density PLD

2128vL_02

1

Features

• SuperFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible

with ispLSI 2128V and 2128VE Devices

• 2.5V LOW VOLTAGE 2128 ARCHITECTURE

— Interfaces with Standard 3.3V Devices (Inputs and

I/Os are 3.3V Tolerant)

— 125 mA Typical Active Current

—

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-

OR Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram*

Description

The ispLSI 2128VL is a High Density Programmable

Logic Device available in 128 and 64 I/O-pin versions.

The device contains 128 Registers, eight Dedicated

Input pins, three Dedicated Clock Input pins, two dedi-

cated Global OE input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 2128VL fea-

tures in-system programmability through the Boundary

Scan Test Access Port (TAP) and is 100% IEEE 1149.1

Boundary Scan Testable. The ispLSI 2128VL offers non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2128VL device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128VL device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Global Routing Pool (GRP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

Logic

Array

GLB

DQ

DQ

DQ

DQ

0139A/2128VL

C7

C6

C5

C4

C3

C2

C1

C0

D3

D2

D1

D0

D7

D6

D5

D4

B4

B5

B6

B7

B0

B1

B2

B3

A0

A1

A2

A3

A4

A5

A6

A7

*128 I/O version shown

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com