LTC1267 datasheet(13/16 Pages) LINER

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LTC1267

LTC1267-ADJ/LTC1267-ADJ5

APPLICATIO S I FOR ATIO

and inductor core losses, generally account for less

than 2% total additional loss.

Auxiliary Windings––Suppressing Burst Mode

Operation

The LTC1267 synchronous switch removes the normal

limitation that power must be drawn from the inductor

primary winding in order to extract power from auxiliary

windings. With synchronous switching, auxiliary outputs

may be loaded without regard to the primary output load,

providing that the loop remains in continuous mode

operation.

Burst Mode operation can be suppressed at low output

currents with a simple external network which cancels the

25mV minimum current comparator threshold. This tech-

nique is also useful for eliminating audible noise from

certain types of inductors in high current (IOUT > 5A)

applications when they are lightly loaded.

An external offset is put in series with the Sense – pin to

subtract from the built-in 25mV offset. An example of this

technique is shown in Figure 7. Two 100

Ω resistors are

inserted in series with the sense leads from the sense

resistor.

RSENSE

COUT

LTC1267 • F07

SENSE+

LTC1267

1000pF

SENSE–

100

Ω

100

Ω

Figure 7. Suppressing Burst Mode Operation

With the addition of R3 a current is generated through R1

causing an offset of:

VOFFSET = VOUT

)

) R1

R1 + R3

If VOFFSET > 25mV, the built-in offset will be cancelled and

Burst Mode operation is prevented from occurring. Since

VOFFSET is constant, the maximum load current is also

decreased by the same offset. Thus, to get back to the

same IMAX, the value of the sense resistor must be

reduced:

RSENSE ≈

Ω

IMAX

To prevent noise spikes from erroneously tripping the

current comparator, a 1000pF capacitor is needed across

Sense+ and Sense– pins.

Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1267. These items are also illustrated graphically in

the layout diagram of Figure 8. In general each block

should be self-contained with little cross coupling for best

performance. Check the following in your layout:

1. Are the signal and power grounds segregated? The

LTC1267 signal ground must return to the (–) plate of

COUT. The power ground returns to the source of the

N-channel MOSFET, anode of the Schottky diode,

and (–) plate of CIN, which should have as short lead

lengths as possible.

2. Does the LTC1267 Sense – pin connect to a point close

to RSENSE and the (+) plate of COUT? In adjustable

applications the resistive divider R1 and R2 must be

connected between the (+) plate of COUT and signal

ground.

3. Are the Sense – and Sense + leads routed together with

minimum PC trace spacing? The 1000pF capacitor

between the two Sense pins should be as close as

possible to the LTC1267. Up to 100

Ω may be placed in

series with each Sense lead to help decouple the Sense

pins. However, when these resistors are used the

capacitor should be no larger than 1000pF.

4. Does the (+) plate of CIN connect to the source of the

P-channel MOSFET as closely as possible? An addi-

tional 0.1

µF ceramic capacitor between VIN and power

ground may be required in some applications.

5. Is the VCC decoupling capacitor connected closely

between the VCC pins of the LTC1267 and power

ground? This capacitor carries the MOSFET driver peak

currents.

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