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UPD98405 Datasheet(PDF) 20 Page - NEC

Part # UPD98405
Description  155M ATM INTEGRATED SAR CONTROLLER
PDF  64 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD98405 Datasheet(HTML) 20 Page - NEC

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Data Sheet S12689EJ2V0DS00
20
µµµµPD98405
1.4 PMD Interface Signals (internal PHY mode, PHM of GMR register = 0)
The PMD interface is used to connect a module such as an optical transceiver/receiver.
Pin Name
Pin No.
I/O
I/O Level
Function
RDIT
278
I
P-ECL
True (+)
Receive serial data input.
Pull up this pin when it is not used.
RDIC
277
I
P-ECL
complement
(–)
Receive serial data input.
Pull down this pin when it is not used.
RCIT (shared
with FULL_B)
249
I
P-ECL
True (+)
Receive serial clock input.
This pin is used when an external clock recovery/synthesizer is
connected (PLL of GMR register = 1).
Pull up this pin when it is not used.
RCIC (shared
with
EMPTY_B)
248
I
P-ECL
complement
(–)
Receive serial clock input.
This pin is used when an external clock recovery/synthesizer is
connected (PLL of GMR register = 1).
Pull down this pin when it is not used.
REFCLK
(shared with
PHINT_B)
268
I
TTL
Reference clock.
This pin inputs a system clock (19.44 MHz) to the internal clock
recovery/synthesizer.
Pull up this pin when it is not used.
TDOT
273
O
P-ECL
True (+)
Transmit serial data output.
TDOC
274
O
P-ECL
complement
(–)
Transmit serial data output.
TFKT (shared
with Rx0)
242
I
P-ECL
True (+)
Transmit serial clock input.
This pin is used when an external clock recovery/synthesizer is
connected (PLL of GMR register = 1).
Pull up this pin when it is not used.
TFKC
(shared with
Rx1)
241
I
P-ECL
complement
(–)
Transmit serial clock input.
This pin is used when an external clock recovery/synthesizer is
connected (PLL of GMR register = 1).
Pull down this pin when it is not used.
PHYALM
(shared with
PHR/W_B)
266
O
TTL
PHY layer alarm detection signal.
This signal is asserted active (high) when any of the internally
monitored error statuses (CMDARM, LOS, OOF, LOF, LOP,
OCD, LCD, Line AIS, Path AIS, Line RDI, and Path RDI) is
detected. The error status to be reported can be selected by
using the internal AMR1 and AMR2 registers. One or more
error statuses can be selected.
SD
(shared with
PHCE_B)
267
I
TTL
Signal detect.
This pin inputs the signal detect signal (when LOS is detected,
etc.) of the PMD device. When a low level is input to this pin,
the
µPD98405 assumes LOS detection.
Pull up this pin when it is not used.



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