RT9480 datasheet(14/16 Pages) RICHTEK

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RT9480

DS9480-04

December 2014

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 1. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WQFN-24L 4x4 package, the thermal resistance,

θJA, is

°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25

°C can

be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (28°C/W) = 3.57W for

WQFN-24L 4x4 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 1 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Consideration

The PCB layout is an important step to maintain the high

performance of the RT9480.

Both the high current and the fast switching nodes demand

full attention to the PCB layout to save the robustness of

the RT9480 through the PCB layout. Improper layout might

show the symptoms of poor line or load regulation, ground

and output voltage shifts, stability issues, unsatisfying

EMI behavior or worsened efficiency.For the best

performance of the RT9480, the following PCB layout

guidelines must be strictly followed.



Place the input and output capacitors as close as

possible to the input and output pins respectively for

good filtering.



Care should be taken for a proper thermal layout. Wide

traces, connecting with vias through the layers, provides

a proper thermal path to sink the heat energy created

from the device and inductor. Keep the main power traces

as wide and short as possible. Recommend as below :

VBUS trace > 40mil;

VBAT trace > 80mil;

LXBST trace > 80mil;

VMID trace > 40mil;

USBOUT1 trace > 80mil;

USBOUT2 trace > 40mil.



The switching node area connected to LX and inductor

should be minimized for lower EMI.



Connect the GND pin, PGNDBST pin and Exposed Pad

together to a strong ground plane for maximum thermal

dissipation and noise protection.



Directly connect the output capacitors to the feedback

network of each channel to avoid bouncing caused by

parasitic resistance and inductance from the PCB trace.

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