In Figure 3b, the mux selects the signal from one of

three input channels: RPS, FPS1, and FPS2. The PGA

then amplifies or attenuates the input signal according

to the signal power-class level and the transmission

mode (forward or reverse) (Table 1). Three gain set-

tings are provided in the PGA: -0.53, -0.44, and -6. The

voltage range at the internal node PSOUT is equal to

the ADC’s input range.

After the PGA, the signal is fed to a peak detector,

which tracks the input and holds the positive peak volt-

age until the ADC starts a conversion.

Mobile-Radio Analog Controller

8

_______________________________________________________________________________________

+

–

PSBIAS

D1

1k

50

Ω

R3

R1

RF INPUT

R5

300

Ω

1.87V

C3

10pF

RPS

FPS1

FPS2

R2

50

Ω

C2

10pF

C1

10pF

AGND

AGND

C4

1nF

50

Ω TRANSMIT LINE

OR 22nH INDUCTOR

Figure 3a. External Circuit for Envelope Detection

(one channel)

100

µA

PSOUT

PGA

FPS1

FPS2

RPS

Figure 3b. Power-Sense Block

Table 1. Data-Byte Definitions

NAME

D [7:0]

0 0 0

XDAC

Write [7,6]:

[5:0]:

0 0 1

SDAC

Write

[7]:

[6:0]:

A [2:0]

0 1 0

KDAC

Write

[7]:

[6:0]:

0 1 1

GDAC

Write [7,6]:

[6:0]:

1 1 1

ADC

Read [7:0]:

1 1 0

1 0 1

1 0 0

DESCRIPTION

Reserved

XDAC value [5:0]; LSB is bit 0, binary.

F/R bit, defines forward or reverse power-sense measurement

0 = Reverse power-sense measurement; RPS pin

1 = Forward power-sense measurement; FPS1/FPS2 pin

SDAC value [6:0]; LSB is bit 0, binary.

ADC channel selection:

0 = Power sense or RSSI via peak-hold circuit connected to ADC (CH0)

1 = RSSI pin connected to ADC directly (CH1)

KDAC value [6:0]; LSB is bit 0, binary.

Power class:

00 = Class 1

01 = Class 2

10 = Class 3

11 = Class 4

GDAC value [5:0]; LSB is bit 0, binary.

ADC value [7:0]; LSB is bit 0, binary.

Reserved

Reserved

Reserved