SM34 Data Sheet #:

TM095

Page 12

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Detailed Description continued

Output Signals and Frequency

Output 1 is the primary output, and in locked mode is synchronized to the selected reference. Output 1 may be any of the

following frequencies: 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz or 77.76 MHz.

8k_Out is available as a frame reference or synchronization signal for cross-coupled pairs of SM34 devices operated in master/

slave mode. In master mode, 8k_Out is synchronized to the selected reference. In slave mode, 8k_Out is in phase with the

M/S REF

offset by the value written to the

Phase_offset register (+31.75 to -32nS, with .25nS resolution). 8k_Out may be a 50% duty cycle

signal, or variable high-going pulse width, as determined by the

Ctl_Mode and Fr_Pulse_Width registers. In variable pulse width

mode, the width may be from 1 to 15 multiples of the

Output 1 cycle time. See Register Descriptions and Operation section.

BITS_Clk is the BITS clock output at either 1.544 MHz or 2.048 MHz. It is selected by the BITS_SEL input and its state may be

read in bit 3 of the Ctl_Mode register. When BITS_SEL = 1, the BITS frequency is 1.544 MHz, and when BITS_SEL = 0, the BITS

frequency is 2.048 MHz.

Interrupts

The SM34 module supports eight different interrupts and appears in

INTR_EVENT (0x12) register. Each interrupt can be

individually enabled or disabled via the

INTR_ENABLE (0x13) register. Each bit enables or disables the corresponding interrupt from

asserting the

SPI_INT pin. Interrupt events still appear in the INTR_EVENT (0x12) register independent of their enable state. All

interrupts are cleared once

INTR_EVENT (0x12) register is read. The interrupts are:

•

Any reference changing from available to not available

•

Any reference changing from not available to available

•

M/S REF changing from activity to no activity

•

M/S REF changing from no activity to activity

•

DPLL Mode status change

•

Reference switch in automatic reference selection mode

•

Loss of Signal

•

Loss of Lock

Interrupts and Reference Change in Autonomous Mode

Interrupts can be used to determine the cause of a reference change in autonomous mode. Let us assume that the module is

currently locked to

REF1. The module switches to REF2 and SPI_INT pin is asserted. The user reads the INTR_EVENT (0x12)

register.

If the module is operating in autonomous non-revertive mode, the cause can be determined from bits 4, 5, 6 and 7. Bit 5 is set to

indicate Active reference change. If Bit 6 is set then the cause of the reference change is Loss of Active Reference. If Bit 7 is set then

the cause of the reference change is a Loss of Lock alarm on the active reference.

If the module is operating in autonomous revertive mode, the cause can be determined from bits 1, 4,5, 6 and 7. Bit 5 is set to

indicate Active reference change. If Bit 6 is set then the cause of the reference change is Loss of Active Reference. If Bit 7 is set

then the cause of the reference change is a Loss of Lock alarm on the active reference. If Bit 1 is set then the cause of the reference

change is the availability of a higher priority reference.

Note: The DPLL Mode Status Change bit (Bit 4) is also set to indicate a change in DPLL_STATUS (0x11) register, during an

interrupt caused by a reference change. The data in

DPLL_STATUS (0x11) register however is not useful in determining the cause of

a reference change. This is because bits 0-2 of this register always reflects the status of the current active reference and hence cannot

be used to determine the status of the last active reference.

Interrupts in Manual Mode

In manual operating mode, when the active reference fails due to a Loss of Signal or Loss of Lock alarm, an interrupt is generated.

For example, in case of a Loss of Signal, bits4 and 6 of

INTR_EVENT (0x12) register would be set to indicate Loss of Signal and

DPLL Mode Status Change. The user may choose to read the

DPLL_STATUS (0x11) register, though in manual mode bit6 of INTR_

EVENT (0x12) register is a mirror of bit0 of DPLL_STATUS (0x11) register. This holds true for a Loss of Lock alarm, where bit7 of

INTR_EVENT (0x12) register is a mirror of bit1 of DPLL_STATUS (0x11) register.

Internal Clock Calibration

The internal clock may be calibrated by writing a frequency offset v.s. nominal frequency into the Calibration register. This

calibration is used by the synchronization software to create a frequency corrected from the actual internal clock output by the value

written to the Calibration register. See register descriptions.