SM34 Data Sheet #:

TM095

Page 16

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Register Descriptions and Operation continued

Phase_Offset, 0x0e (R/W)

Bit 7 ~ Bit 0

The2’scomplementvalueofphaseoffsetbetweenMasterOutputmoduleandSlaveOutputmodule,rangesfrom-32nSto+31.75nS

PositiveValue:MasterOutputrisingedgeleadsSlaveOutput

NegativeValue:MasterOutputrisingedgelagsSlaveOutput

Inslavemode,theslave’soutputsmaybephaseshifted-32nSto+31.75nSin.25nSincrements,relativetoM/Sac-

cordingtothecontentsofthePhase_Offsetregister,tocompensateforthepathlengthoftheM/StoM/Sconnection.

Ifaphaseoffsetisused,thenthetwoSM34deviceswouldtypicallybewrittentotheappropriatephaseoffsetval-

uesfortherespectivepathlengthsofeachMastertoSlaveconnection,toensurethatthesamerelativeoutputsignal

phaseswillpersistthroughmaster/slaveswitches.

Calibration, 0x0f (R/W)

Bit 7 ~ Bit 0

2’scomplementvalueoflocaloscillatordigitalcalibrationin0.05ppmresolution

Todigitallycalibratethefreerunningclocksynthesizedfromtheinternalclock,thisregisteriswrittenwithavaluecor-

respondingtotheknownfrequencyoffsetoftheoscillatorfromthenominalcenterfrequency.

Fr_Pulse_Width, 0x10 (R/W)

Bit 7 ~ Bit4

Bit 3 ~ Bit 0

Reserved

PulsewidthforM/Sclockoutput,

1-15multiplesoftheSync_Clkclockperiod.

BITS4and5oftheCtl_ModeregisterdetermineiftheM/S8kHzoutputis50%dutycycleorpulsed(highgoing)

outputs.Whentheyarepulsed,theFr_Pulse_Widthregisterdeterminesthewidth.Widthistheregistervaluemultipleof

theSync_Clkclockperiod.Validvaluesare1-15.

Resetdefaultis0001.Writingto0000mapsto0001.

DPLL_Status, 0x11 (R)

Bit 7 ~Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

HoldOver

HoldOver

Locked

LossofLock

LossofSignal

Build

Available

1:Locked

1:LossofLock

1:Noactivity

Complete

1:Avail.

0:Notlocked

0:Nolossoflock

onactive

1:Complete

0:Notavail.

reference

0:Incomplete

0:Activeref-

erencesignal

present

Bit0indicatesthepresenceofasignalontheselectedreference.

Bit1indicatesalossoflock(LOL).Lossoflockwillbeassertediflockisnotachievedwithinthespecifiedtimeforthe

stratumlevelofoperation,orlockislostafterbeingestablishedpreviously.LOLwillnotbeassertedforautomatic

referenceswitches.

Bit2indicatessuccessfulphaselock.Itwilltypicallybesetin<700secondsforStratum3withagoodreference.

Itwillindicate“notlocked”iflockislost.

Bit3indicatesifaHoldOverhistoryisavailable.

Bit4indicateswhenanewHoldOverhistoryhasbeensucessfullybuiltandtransferredtotheactiveHoldOver

history.SeeDetailedDescriptionsectionunderInterruptsandReferenceChangeinAutonomousModeandInterrupts

inManualMode