MAX5913 datasheet(3/20 Pages) MAXIM

3 / 20 page

+48V Quad Hot-Swap Controllers For

Power-Over-LAN

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ELECTRICAL CHARACTERISTICS (continued)

(VCC = VCSP_ = +48V, AGND = DGND = 0, VDD = +3.3V, VRLY = +12V, TA = -40°C to +85°C, unless otherwise noted. Typical values

are at VCC = VCSP_ = +48V and TA = +25°C.) (Note 3)

Note 1: See Typical Operating Characteristics for Current-Limit Foldback, and refer to Current Sensing and Regulation section.

Note 2: The resistor at RTIM can range from 2k

Ω to 40kΩ.

Note 3: Limits are 100% tested at TA = +25°C and TA = +85°C. Limits at -40°C are guaranteed by design and characterization, but

are not production tested.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

During current regulation

µA

VON = 0

Gate Discharge Current

IGATE,DIS

(VCSP_ - VDRAIN_) > VFC

Source-Gate Clamp Voltage

VSGZ

VOUT_ = 0, force 30mA into GATE_, measure

VGATE - VOUT

16.5

OPEN-CIRCUIT DETECTOR

Open-Circuit Current-Threshold

Voltage

VOC

Minimum

∆V across RSENSE to detect an

open circuit

1.5

4.5

Delay to Open-Circuit Detect

tOC

(Figure 2)

450

900

1350

Deglitch Delay

tLPFD

(VCSP_ - VDRAIN

__) < VOC (Figure 2)

106

204

302

RELAY DRIVERS

Maximum Low Voltage (MAX5913)

VRLOW

RLYON = high, IRLYD_ = 100mA

0.5

Relay Pullup Current (MAX5914)

IRPLUP

RLYON = high, VRLYD_ = 0

0.3

0.8

1.3

Clamp Diode Voltage

VRCLAMP

Force 100mA into RLYD, measure VRLYD -

VRLY

Relay Output Leakage

RLYON_ = low, VRLYD_ = VRLY

1µA

TIMING

RRTIM = 2k

Ω

4.8

6.4

8.0

RRTIM = 40k

Ω

128

180

Short-Circuit and Startup Timer

(Note 2)

On time for continuous

overcurrent conditions

RRTIM =

∞

3.2

6.4

9.6

DC = logic low

DC = logic high

Auto-Retry Duty Cycle

DC = floating

Port Turn-ON Delay

tON_DEL

VON = 3.3V (Figure 3)

12.8

25.6

38.4

Relay Turn-OFF Delay

tOFF_DEL

After RLYON_ goes low (Figure 3)

1.6

3.2

4.8

DIGITAL INTERFACE

DC Pin Input Voltage High

VIH_DC

+1.8V

≤ VDD ≤ +3.7V

0.7 x VDD

DC Pin Input Voltage Low

VIL_DC

+1.8V

≤ VDD ≤ +3.7V

0.3 x VDD

DC Pin Input Impedance

RIN_DC

Ω

Logic Input High

VIH

+1.8V

≤ VDD ≤ +3.7V

0.8 x VDD

Logic Input Low

VIL

+1.8V

≤ VDD ≤ +3.7V

0.3 x VDD

Logic Input Leakage

1µA

FAULT Output Voltage Low

VFL

ISINK = 4mA

0.4

FAULT High Input Leakage

1µA

Logic Output Voltage High

VOH

STAT_ outputs sourcing 0.5mA

VDD - 0.4

Logic Output Voltage Low

VOL

STAT_ outputs sinking 0.5mA

0.4

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