BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION)

S-8213 Series

Seiko Instruments Inc.

12

3. Test mode

The test mode can be set by retaining the VDD pin voltage 4.0 V or more higher than the VC1 pin voltage for 20 ms or

longer. The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is

decreased to the same voltage as that of the VC1 pin voltage.

After that, the latch for retaining the test mode is reset and the S-8213 Series exits from test mode under the overcharge

status.

Pin voltage

CO pin

(Active "H")

Test mode

VDD pin voltage

4.0 V or

more

Battery voltage

VC1 pin voltage

(n = 1 to 3)

32 ms typ.

CO pin

(Active "L")

2.0 ms typ.

Figure 11