BATTERY PROTECTION IC FOR 2-SERIES OR 3-SERIES-CELL PACK

S-8253C/D Series

Seiko Instruments Inc.

13

6. Resistance between VMP and VDD, Resistance between VMP and VSS

(Test Condition 6, Test Circuit 2)

Confirm that V1

= V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), S1 = ON, and S2 = OFF (this

status is referred to as the initial status).

and S2 are switched to OFF and ON, respectively, starting at the initial status.

=

V2

= 1.8 V (S-8253C Series) or V1 = V2 = V3 = 1.8 V (S-8253D Series) are set starting at the initial status.

7. CTL Pin Input Voltage “H”

(Test Condition 7, Test Circuit 1)

Confirm that V1

= V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0 V, and the

COP pin and DOP pin are low (this status is referred to as the initial status).

after the voltage of V4 has been gradually increased starting at the initial status.

8. CTL Pin Input Voltage “L”

(Test condition 7, Test circuit 1)

Confirm that V1

= V2 = 3.5 V (S-8253C Series), V1 = V2 = V3 = 3.5 V (S-8253D Series), V4 = 0 V, V5 = 0.35 V, and

the COP pin and DOP pin are high (this status is referred to as the initial status).

after the voltage of V4 has been gradually increased starting at the initial status.

9. CTL Pin Current “H”, CTL Pin Current “L”

(Test Condition 8, Test Circuit 3)

= V2 = 3.5 V (S-8253C

Series), V1

current that flows through the CTL pin when S3

= OFF and S4 = ON after that.