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CMX148 Datasheet(PDF) 49 Page - CML Microcircuits |
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CMX148 Datasheet(HTML) 49 Page - CML Microcircuits |
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49 / 75 page ![]() PMR Audio and Data Processor CMX148 © 2010 CML Microsystems Plc 49 D/148/6 8.1.24. Modem Control - $C7 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SynC SynD SynT 0 0 En_ RAW Last Tx Data Inter- leave MSK/FFSK Message Format 0 0 User Bit Scramble Seed This register configures the way the CMX148 handles MSK data in Tx and Rx modes. b15 SynC detect (MSK/FFSK) 0 = off 1 = enabled b14 SynD detect (MSK/FFSK) 0 = off 1 = enabled b13 SynT detect (MSK/FFSK) 0 = off 1 = enabled note: SynC, SynD and SynT patterns are defined in Program Block P0.0-3 b12 reserved 0 b11 reserved 0 b10 En_RAW: 0 = data packetising on 1 = raw data mode This selects the raw or formatted mode for type 0 MSK/FFSK or DSC data. MSK/FFSK Receive mode: b10 = 1: device will look for the programmed Frame Sync. pattern, raise an interrupt (if enabled) and decode the following data 16 bits at a time, making them available in Rx Data 1 register ($C5). b10 = 0: device will look for a complete Frame Head before raising an interrupt (if enabled) and then decode the following data in accordance with the received message format. The Frame Head Control Field bytes, user data and any CRC will be presented in the appropriate Rx Data registers ($C5 and $C9). MSK/FFSK Transmit mode: b10 = 1: device will transmit data 16 bits at a time from Tx Data 1 register ($CA). Bit and frame sync pattern generation and all formatting of the data have to be performed by the host in this case. b10 = 0: device will transmit the programmed bit and frame sync patterns followed by a Frame Head containing the information supplied in bits 7–0 of this register and the 2 bytes in Tx Data 1 register ($CA). Subsequently the host must supply data when requested to complete the transmission of the Frame Head and Data Block. b9 Last Tx data: This is only valid when transmitting data with Formats 0, 2 or 3 in MSK/FFSK modes and indicates to the CMX148 that it can cease modulation. The host must set this bit to 1 immediately after the interrupt for ‘load more data’ occurs ($C6 bit 6). In receive, or when transmitting other message formats, this bit must be cleared to 0. b8 Interleave: 0 = off 1 = on This bit selects if Frame Headers in MSK/FFSK modes will be interleaved or not. b7-5 Data Format: b7 b6 b5 Format Message Format 0 0 0 0 Raw Data (En_RAW = 1) 0 0 1 1 Frame Head only, no payload 0 1 0 2 Frame Head + Unsized payload of raw 16 bit words 0 1 1 3 Frame Head + Unsized payload with FEC 1 0 0 4 Frame Head + Sized payload with FEC + CRC 1 0 1 5 Frame Head + Sized payload with FEC + CRC + interleaving All other patterns - reserved b4 reserved, clear to 0. b3 reserved, clear to 0. b2 User bit. May be freely used by the host in MSK/FFSK modes. This bit has no effect on the message format or encoding and will be reported in the Rx Data 1 register for the receiving host to use as appropriate. This bit could be used to indicate a special message, e.g. one containing handset or channel set-up information. |
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