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CMX148 Datasheet(PDF) 59 Page - CML Microcircuits |
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CMX148 Datasheet(HTML) 59 Page - CML Microcircuits |
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59 / 75 page ![]() PMR Audio and Data Processor CMX148 © 2010 CML Microsystems Plc 59 D/148/6 8.2.4. Program Block 3 – AuxDAC, RAMDAC and Clock Control This block is divided into two sections to facilitate loading the RAMDAC buffer. Set bit 15 to 1 and clear bit 10 to 0 to start the loading sequence from P3.0. Set both bits 15 and 10 to start the loading sequence from P3.11 (RAMDAC data). The Internal clk dividers only require modification if a non-standard XTAL frequency is used (see Table 1 ) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P3.0 1 1 1 1 0 0 0 0 AuxADC1 Average Counter P3.1 0 1 1 1 0 0 0 0 reserved P3.2 0 1 1 1 GP Timer value in IDLE mode P3.3 0 1 1 1 VCO output and AUX clk divide in IDLE mode P3.4 0 1 1 1 Ref clk divide in Rx or Tx mode P3.5 0 1 1 1 PLL clk divide in Rx or Tx mode P3.6 0 1 1 1 VCO output and AUX clk divide in Rx or Tx mode P3.7 0 1 1 1 0 0 0 0 Internal ADC / DAC clk divide in Rx or Tx mode P3.8 0 1 1 1 0 0 0 0 ADC Internal Control 1 P3.9 0 1 1 1 0 0 0 0 ADC Internal Control 2 P3.10 0 1 1 1 0 0 0 0 0 0 0 0 ADC Internal Control 3 P3.11 1 1 1 1 0 1 User Defined RAMDAC data 0 P3.xx 0 1 1 1 0 1 User Defined RAMDAC data xx P3.74 0 1 1 1 0 1 User Defined RAMDAC data 63 Default Values: P3.0 $F000 P3.1 $7000 P3.2 - P3.7: see Table 1 P3.8 $7000 P3.9 $7101 P3.10 $7002 P3.11 - P3.74: see Table 9 Table 9 RAMDAC Values Default RAMDAC Contents After Reset (hex) 0 000 1 001 2 003 3 006 4 00A 5 010 6 017 7 01F 8 028 9 033 10 03E 11 04B 12 059 13 068 14 078 15 089 16 09A 17 0AD 18 0C1 19 0D5 20 0EA 21 100 22 116 23 12D 24 145 25 15D 26 175 27 18E 28 1A7 29 1C0 30 1D9 31 1F3 32 20C 33 226 34 23F 35 258 36 271 37 28A 38 2A2 39 2BA 40 2D2 41 2E9 42 2FF 43 315 44 32A 45 33E 46 352 47 365 48 376 49 387 50 397 51 3A6 52 3B4 53 3C1 54 3CC 55 3D7 56 3E0 57 3E8 58 3EF 59 3F5 60 3F9 61 3FC 62 3FE 63 3FF |
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