FX929B datasheet(23/48 Pages) CMLMICRO

23 / 48 page

4-Level FSK Modem Data Pump

FX929B

D/929B/1

Mode

Hold

Level Track

Lossy Peak Detect

Slow Peak Detect

In normal use the LEVRES bits should be set to '0 1' (Level Track), the other modes are intended for special

purposes, for device testing, or are invoked automatically during an AQLEV sequence.

In ‘Slow Peak Detect’ modes the positive and negative excursions of the received signal (after filtering) are

measured by peak rectifiers driving the DOC1 and DOC2 capacitors to establish the amplitude of the signal

and any dc offset wrt VBIAS. This mode provides good overall performance, particularly when acquiring level

information at the start of a received message, but does not work well with certain long sequences of repeated

data byte values. It is also susceptible to large amplitude noise spikes such as can be generated during deep

fades.

The ‘Lossy Peak Detect’ mode is similar to ‘Slow Peak Detect’ but the capacitor discharge time constant is

much shorter, so this mode is not suitable for normal data reception and is only used within part of the

automatic AQLEV acquisition sequence.

In ‘Level Track’ mode the DOC capacitor voltages are slowly adjusted by the FX929B in such a way as to

minimise the average errors seen in the received signal. This mode provides the best overall performance,

being much more immune to large amplitude noise spikes than ‘Slow Peak Detect’ and being much less

sensitive to long sequences of repeated data byte values. It does, however, depend on the measured levels

and timing being approximately correct. If either of these is significantly wrong then the correction algorithm

used by the ‘Level Track’ mode can actually drive the voltages on the DOC capacitors away from their

optimum levels.

For this reason the automatic AQLEV acquisition sequence (see 1.6.3) forces the level

measuring circuits into ‘Slow Peak Detect’ mode until a Frame Sync pattern has been found.

The DOC capacitors are isolated from the charging and discharging circuits in ‘Hold mode, allowing the

voltages to float.

Control Register B1, B0: PLLBW - Phase-Locked Loop Modes

These two bits have no effect in transmit mode. In receive mode, they set the 'normal' bandwidth of the Rx

clock extraction Phase Locked Loop circuit. This setting will be temporarily overridden by the automatic

sequencing of an AQSC command.

PLL Mode

Hold

Narrow Bandwidth

Medium Bandwidth

Wide Bandwidth

The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the

frequency of the receiving modem's Xtal are both within ±100ppm of nominal, except at the start of a symbol

clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in section 1.6.3.

FX929B Datasheet(PDF) 23 Page - CML Microcircuits

FX929B Datasheet(HTML) 23 Page - CML Microcircuits

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL