LMP92018

SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

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DAC CONFIGURE

The individual DACs can be enabled by setting a corresponding bit in the 4–bit CDAC word. The CDAC word can

be set and tested via the SPI transactions shown in the following table. The DAC block is described in

PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:16

15:4

3:0

23

22:16

15:4

3:0

READ

1

0011000

x

x

1

0011000

000000000000

CDAC

WRITE

0

0011000

000000000000

CDAC

0

0011000

000000000000

0000

x

Don't care

1: enables DAC corresponding to bit position

CDAC

0: disables corresponding DAC

e.g. CDAC=[0101] enables DAC2 and DAC0

UPDATE ALL DACs

All 4 DAC channels' outputs can be simultaneously set to the same level corresponding to a 10–bit DDATA code.

The sequence in the following table provides a WRITE only functionality. The DAC block is described in

PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:16

15:12

11:2

1:0

23

22:16

15:12

11:2

1:0

WRITE

0

0011001

0000

DDATA

00

0

0011001

0000

0000000000

00

x

Don't care

DDATA

DDATA will be loaded into all all DACs' input registers simultaneously. DDATA is a 10–bit unsigned integer.

GENERAL CONFIGURATION

The device can indicate to the new ADC conversion data availability via the DRDYB pin. This functionality is

enabled by setting the internal DRDY bit. The bit can be set and tested via the SPI transactions shown in the

following table. Details of the DRDYB pin functionality are described in Conversion Sequence and DIGITAL

TEMPERATURE SENSOR

FRAME 1: DIN

FRAME 2: DOUT

Command

Payload

Command

Payload

Bit

→

23

22:16

15:1

0

23

22:16

15:1

0

READ

1

0011110

x

x

1

0011110

000000000000000

DRDY

WRITE

0

0011110

000000000000000

DRDY

0

0011110

000000000000000

0

x

Don't Care

1: Disables the DRDYB pin function

DRDY

0: Enables the DRDYB pin function

GPIO CONFIGURE

Individual bits of the general purpose digital I/O port can be configured to drive (output), or sense (input) only.

Setting a corresponding bit in the 12–bit CGPIO word will enable that pin to drive. The sequences in the following

table provide a READ and WRITE capability for the internal CGPIO register. The GPIO block is described in

GENERAL PURPOSE DIGITAL I/O.

14

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