Reference

AREF

DREF

A

B

C

D

E

SPI Control Word

Device Pin

REF

CREF

LMP92018

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SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

Figure 21. Reference Selector Diagram

Table 2. Reference Selector Functionality

(1 to CLOSE Switch)

Switch

CREF

A

B

C

D

E

000

1

0

0

0

1

001

0

0

0

1

1

010

1

1

0

0

0

011

0

1

0

1

0

100

0

0

0

0

0

101

0

0

1

1

1

110

0

0

0

0

0

111

0

0

0

0

0

GENERAL PURPOSE DIGITAL I/O

The GPIO[11:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the

SPI interface.

The SGPI register content reflects at all times the digital state at the GPIOx device pins. The format of the read

command of the General Purpose Digital I/O is shown in GPI STATE.

The GPIOx pins can be configured as outputs by setting the individual bits in the CGPIO registers. Each bit in

CGPIO register enables corresponding output buffer in the GPIOx port. See GPIO CONFIGURE. Once the drive

is enabled, the logic state at the outputs is dictated by the contents of the CGPO register. See GPO DATA.

The functional diagram of the General Purpose Digital I/O is shown in Figure 22.

Copyright © 2011–2013, Texas Instruments Incorporated

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