VDD/2

Device Pin

+

-

ROUT< 4k

Voltage

Source

INx

Sampling

Switch

ADATA = INT

AREF

x 1023

(

)

LMP92018

SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

www.ti.com

FUNCTIONAL DESCRIPTION

ANALOG SENSE SUBSYSTEM

The device is capable of monitoring up to 8 externally applied voltages. The system is centered around a 10-bit

SAR ADC fronted by an 8-input mux.

Sampling and Conversion

acquired, the stored charge is measured using the Successive Approximation Register (SAR) method. The timing

of the internal state machine is governed by the user defined signals CSB and SCLK. The sequence of the

events is described in Conversion Sequence.

Attention should be paid to the output impedance of the sensed voltage source and the capacitance present at

the bandwidth and settling time of the input signal. At maximum SPI bus data rate, it is recommended to limit the

output resistance ROUT of the signal source to assure the accuracy of the conversion.

the conversion, unless the SCLK is so slow that the charge is lost due to the internal capacitor's leakage. Under

normal conditions the charge stored is modified only during TRACK period.

Below is a typical ADC output code as a function of input voltage at device pin INx, x=0...7:

(1)

In the expression above AREF is the reference voltage input to the internal ADC. See INTERNAL VOLTAGE

REFERENCE SOURCE.

Figure 13. ADC During TRACK Period

Sampling Transient

As noted in Sampling and Conversion the charge acquired during TRACK period is maintained throughout the

conversion process. Since the successive sample operations will involve different input potentials an

instantaneous current will flow at the beginning of TRACK period. This always leads to temporary disturbance of

the input potential. This current, and resulting disturbance, will vary with the magnitude of the sampled signal and

source impedance ROUT, see Figure 13. If ROUT is excessive, and resulting RC time constant of the input

circuit too long, the preceding sample may affect the new sample's accuracy.

If high ROUT cannot be avoided, another method of improving the acquisitin accuracy is to lengthen the TRACK

time. The ADC TRACK time is fully controlled by the user inputs CSB and SCLK, see Figure 14. The time

frequency of SCLK, subject to limitations on CSB and SCLK timing as shown in Electrical Characteristics .

18

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