VDD/2

15 pF

Device Pin

Sampling

Switch

15 pF

INx

READ IN0

dummy payload

COMMAND

PAYLOAD

CSB

DIN

DOUT

Echo Previous

previous DATA IF ANY

READ IN0

ADATA

1

9

TRACK

HOLD

12

PD

CSB

SCLK

DRDYB

Frame 1

Frame 2

LMP92018

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SNAS514B – NOVEMBER 2011 – REVISED MAY 2013

Conversion Sequence

The ADC conversion sequence and output activity are shown in Figure 14. The ADC readback occupies 2 SPI

frames. The first frame is used to issue a read command and connect the ADC input to the specified device input

pin INx. At the end of the first frame, at the rising edge of the CSB, the ADC sampling capacitor is connected to

the signal source, INx, and the TRACK period begins. The second frame executes the SAR algorithm (the HOLD

period) on the acquired sample and shifts the resulting data out through the DOUT output. The TRACK period

extends for 9 SCLK cycles, then the mux disconnects the sampling capacitor from the signal source, and the

SAR operation begins. The data is shifted out MSB first. Once the SAR operation is completed, the ADC powers

down for the remainder of the second frame.

If DRDYB output pin functionality is enabled, see GENERAL CONFIGURATION, then DRDYB output will be low

while ADC output data is present at DOUT.

If the ADC is not in TRACK or HOLD, the internal PD (Power Down) signal of the ADC is asserted thus powering

down all the active circuits of the ADC, and opening all analog input mux switches. See the PD period in the

Figure 14.

Figure 14. ADC Sequence Diagram

ADC Reference Selection

By default, the ADC operates from the external reference voltage applied at the REF pin of the device. It should

be noted that due to the architecture of the ADC the DC current flowing into the REF input is zero during

be significant. For further details of reference source selection see INTERNAL VOLTAGE REFERENCE

SOURCE

Selection of the ADC reference source automatically dictates the attenuation level of the input signal. Figure 15

shows the ADC input configuration during the TRACK period when the REF pin is chosen as the source of the

this configuration remains as shown in Sampling and Conversion

Figure 15. ADC Sampling when AREF is Externally Supplied

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