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AM4376 Datasheet(PDF) 227 Page - Texas Instruments |
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AM4376 Datasheet(HTML) 227 Page - Texas Instruments |
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227 / 261 page  AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851B – JUNE 2014 – REVISED APRIL 2015 5.12.13.1.2 McSPI—Master Mode Table 5-92. McSPI Timing Conditions—Master Mode LOW LOAD HIGH LOAD TIMING CONDITION PARAMETER UNIT MIN MAX MIN MAX Input Conditions tr Input signal rise time 4 8 ns tf Input signal fall time 4 8 ns Output Condition Cload Output load capacitance 5 25 pF Table 5-93. Timing Requirements for McSPI Input Timings—Master Mode (see Figure 5-108) OPP100 OPP50 NO. LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD UNIT MIN MAX MIN MAX MIN MAX MIN MAX Setup time, SPI_D[x] 4 tsu(SOMI-SPICLK) (1) (SOMI) valid before 3 4.5 4.5 4.5 ns SPI_CLK active edge(2) Hold time, SPI_D[x] 5 th(SPICLK-SOMI) (1) (SOMI) valid after 6 6 6 6 ns SPI_CLK active edge(2) (1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Table 5-94. Switching Characteristics for McSPI Output Timings—Master Mode (see Figure 5-109) OPP100 OPP50 NO. PARAMETER LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(SPICLK) Cycle time, SPI_CLK 20.8 41.6 41.6 41.6 ns Typical Pulse duration, 2 tw(SPICLKL) 0.45P(1) 0.45P(1) 0.45P(1) 0.55P(1) 0.45P(1) 0.45P(1) 0.45P(1) 0.45P(1) ns SPI_CLK low Typical Pulse duration, tw(SPICLKH) 0.45P(1) 0.45P(1) 0.45P(1) 0.55P(1) 0.45P(1) 0.45P(1) 0.45P(1) 0.45P(1) ns SPI_CLK high 3 tr(SPICLK) Rising time, SPI_CLK 3.5 3.5 3.5 3.82 ns tf(SPICLK) Falling time, SPI_CLK 3.5 3.5 3.5 3.44 ns Delay time, SPI_CLK active td(SPICLK- 6 edge to SPI_D[x] (SIMO) -1 4.5 -1 6.5 0 6.5 0 6.5 ns SIMO) transition(2) Delay time, SPI_CS active 7 td(CS-SIMO) edge to SPI_D[x] (SIMO) 4.5 6.5 6.5 6.5 ns transition(2) Mode 1 A - 4.2(4) A - 4.2(4) A - 5.2(4) A - 5.2(4) ns Delay time, SPI_CS and 3(3) 8 td(CS-SPICLK) active to SPI_CLK Mode 0 first edge B - 4.2(5) B - 4.2(5) B - 5.2(5) B - 5.2(5) ns and 2(3) Mode 1 B - 4.2(5) B - 4.2(5) B - 5.2(5) B - 5.2(5) ns Delay time, and 3(3) 9 td(SPICLK-CS) SPI_CLK last edge Mode 0 to SPI_CS inactive A - 4.2(4) A - 4.2(4) A - 5.2(4) A - 5.2(4) ns and 2(3) (1) P = SPI_CLK period. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. (3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable: – SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3). – SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2). Copyright © 2014–2015, Texas Instruments Incorporated Specifications 227 Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 |
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