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AM4376 Datasheet(PDF) 230 Page - Texas Instruments |
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AM4376 Datasheet(HTML) 230 Page - Texas Instruments |
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230 / 261 page  QSPI_CSn QSPI_CLK QSPI_D[3:0] n-1 n-2 Command Command 1 Read Data Read Data 0 1 3 2 4 6 6 5 8 7 8 7 max min AM4376, AM4377, AM4378, AM4379 SPRS851B – JUNE 2014 – REVISED APRIL 2015 www.ti.com 5.12.14 Quad Serial Port Interface (QSPI) The Quad SPI (QSPI) module allows single, dual or quad read access to external SPI devices. This module provides a memory mapped register interface, which provides a direct interface to access data from external SPI devices and to simplify software requirements. It functions as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories. General SPI features: • Programmable clock divider • Six pin interface (QSPI_CLK, QSPI_D0, QSPI_D1,QSPI_D2,QSPI_D3, QSPI_CS0) • One external chip select signal • Support for 3-, 4- or 6-pin SPI interface • Programmable CS0 to DATA_OUT delay from 0 to 3 QSPI_CLKs • Only supports SPI MODE 3 NOTE For more information, see the Quad Serial Port Interface section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual (SPRUHL7). Table 5-95 displays the switching characteristics for the Quad SPI module. Table 5-95. QSPI Switching Characteristics (see Figure 5-110 and Figure 5-111) OPP100 OPP50 NO. PARAMETER MIN MAX MIN MAX UNIT 1 tc(QSPI_CLK) Cycle time, QSPI_CLK 20.8(1) 20.8(1) ns 2 tw(QSPI_CLKL) Pulse duration, QSPI_CLK low 9.77(1) 9.77(1) ns 3 tw(QSPI_CLKH) Pulse duration, QSPI_CLK high 9.77(1) 9.77(1) ns 4 td(CS-QSPI_CLK) Delay time, QSPI_CSn active edge to M*P+5(2)(3) M*P+5(2)(3) ns QSPI_CLK transition 5 td(QSPI_CLK- Delay time, QSPI_CLK transition to M*P+5(2)(3) M*P+5(2)(3) ns QSPI_CSn) QSPI_CSn inactive edge 6 td(QSPI_CLK-D1) Delay time, QSPI_CLK active edge to 0 5.5 0 5.5 ns QSPI_D[0] transition 7 tsu(D-QSPI_CLK) Setup time, QSPI_D[3:0] valid before active 8.5 8.5 ns QSPI_CLK edge 8 th(QSPI_CLK-D) Hold time, QSPI_D[3:0] valid after active 0 0 ns QSPI_CLK edge (1) Maximum supported frequency is 48 MHz. (2) P = QSPI_CLK period. (3) M = Programmable via Data Delay Zero (DD0) register. Figure 5-110. QSPI Read Active High Polarity 230 Specifications Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 |
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